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参数资料
| 型号： | CXA3266Q |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封装： | PLASTIC, QFP-48 |
| 文件页数： | 29/62页 |
| 文件大小： | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
- 35 -
UNLOCK Timing
The unlock detect output is an open collector. When unlock detect output S1 goes High, the current I1 is pulled in.
The UNLOCK sensitivity can be adjusted by connecting external resistors (R1, R2) and a capacitor (C) to this
output pin appropriately and changing these values. Operation during three modes is described below.
CASE 1 : When there is no phase difference, that is to say, when the PLL is locked.
The S1 signal is Low and the S2 signal is High.
The UNLOCK output remains Low.
CASE 2 : When there is a phase difference, that is to say, when the S1 signal goes High and Low as shown in
the figure below, the fall slew rate of the S2 signal is determined by the current I1 flowing into that open
collector. Therefore, increasing the resistance R1 causes the S2 signal fall slew rate to become slower.
Also, since the S2 signal rise slew rate is determined by the current I2, reducing the resistance R2
causes the S2 signal rise slew rate to become faster. If this integrated S2 signal does not fall below the
threshold level of the next inverter, the UNLOCK signal stays Low, and the PLL is said to be locked.
CASE 3 : However, even if a phase difference exists as shown above, if the resistance R1 is reduced, the
current I1 flowing into the open collector increases, and the S2 signal fall slew rate becomes faster.
Also, if the resistance R2 is increased, the S2 signal rise slew rate becomes slower. If this integrated
S2 signal falls below the threshold level of the next inverter, the UNLOCK signal goes from Low to
High, and the PLL is said to be unlocked.
unlock
detect
UNLOCK
VCC
Signal from
phase comparator
C
R1
R2
S2
I2
I1
S1
Outside the IC
Inside the IC
S1
S2
UNLOCK
threshold
level
S1
S2
UNLOCK
threshold
level
S1
S2
UNLOCK
threshold
level
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