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参数资料
| 型号： | CXA3266Q |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封装： | PLASTIC, QFP-48 |
| 文件页数： | 61/62页 |
| 文件大小： | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
- 8 -
5VCO
I
TTL
External VCO input.
Programmable counter test input
(controlled by a control register).
When using the VCO TTL input,
open the Pin 3 VCOH and Pin 4
VCOL PECL inputs.
6HOLD
I
TTL
Phase detector hold signal input.
When this pin is High, the phase
detector is stopped and the VCO
oscillation frequency is held. This is
used when the HSYNC cycle is
temporary disrupted.
Fix Low when not used.
(See the HOLD Timing Chart on
Page 29 to 32.)
9SYNC
I
TTL
Sync input.
When using the SYNC TTL input,
open the Pin 7 SYNCH and Pin 8
SYNCL PECL inputs.
The sync signal can be switched
between positive/negative polarity
by an internal register.
10 SENABLE
ITTL
Control signal (enable) for setting the
internal registers.
When SENABLE is Low, registers
can be written ; when High, registers
can be read.
(See the Control Register Table and
Control Timing Chart.)
11 SCLK
I
TTL
Control signal (clock) for setting the
internal registers.
When SENABLE is Low, SDATA is
loaded to the registers at the rising
edge of SCLK.
When SENABLE is High, the register
contents are output from SEROUT at
the falling edge of SCLK.
(See the Control Register Table and
Control Timing Chart.)
12 SDATA
I
TTL
Control signal (data) for setting the
internal registers.
(See the Control Register Table and
Control Timing Chart.)
13 TLOAD
I
TTL
Programmable counter reset.
Register contents can be loaded to
the programmable counter by setting
TLOAD Low.
This pin is normally set to High.
Pin
No.
Symbol I/O
Reference
voltage level
Equivalent circuit
Description
1.5V
IOVCC
IOGND
192
40k
5
6
9
10
11
12
13
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