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参数资料
| 型号： | CXA3266Q |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封装： | PLASTIC, QFP-48 |
| 文件页数： | 17/62页 |
| 文件大小： | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
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Control Register Timing
Write Mode
Many functions of the CXA3266Q can be controlled via a program. Characteristics are changed by setting the
internal control register values via a serial interface comprised of three pins : SENABLE (Pin 10), SCLK (Pin 11)
and SDATA (Pin 12). The write timing diagram is shown below.
Input the 8-bit data and 3-bit register address MSB first to the SDATA pin. Some registers are not 8 bits, but
the data is input aligned with the LSB side in these cases. (See the Register Table.)
SENABLE is the enable signal and is active Low. SCLK is the transfer clock signal, and data is loaded to the IC
at the rising edge. When SENABLE rises, SCLK must be High. (Registers are set at the rising edge of SENABLE.)
When SENABLE falls, SCLK may be either High or Low.
For example, when inputting a 16-bit signal, the initial 5 bits are invalid and the latter 11 bits are valid. That is
to say, the latter 11 bits are loaded to the register.
SENABLE
SDATA
SCLK
SENABLE
SDATA
SCLK
DATA
8 bits
ADDRESS
3 bits
Enlarged
TENS
TENH
TDH
TDS
SENABLE
SDATA
SCLK
DATA
8 bits
address
3 bits
Invalid DATA
5 bits
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