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参数资料
| 型号： | CXA3266Q |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封装： | PLASTIC, QFP-48 |
| 文件页数： | 60/62页 |
| 文件大小： | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
- 7 -
41 VCOVCC —
5V
VCO circuit analog power supply.
Ground this pin to the ground pattern
with a 0.1
F ceramic chip capacitor
as close to the pin as possible.
42 VCOGND —
0V
VCO circuit analog GND.
43 VCOHGND —
0V
VCO SUB analog GND.
47 IRGND
—
0V
IREF analog GND.
48 IRVCC
—
5V
IREF analog power supply.
Ground this pin to the ground pattern
with a 0.1
F ceramic chip capacitor
as close to the pin as possible.
3
VCOH
I
PECL
External VCO input.
Programmable counter test input
(switchable by a control register).
When using the VCO PECL input,
open the Pin 5 VCO TTL input.
4
VCOL
I
PECL
External inverted VCO input.
When open, this pin goes to the PECL
threshold voltage (IOVCC – 1.3V).
Only the Pin 3 VCOH input with
VCOL input open can be also
operated but complementary input is
recommended in order to realize
stable high-speed operation.
7SYNCH
I
PECL
Sync input.
When using the SYNCH PECL input,
open the Pin 9 SYNC TTL input.
The sync signal can be switched
between positive/negative polarity
by an internal register.
8SYNCL
I
PECL
Inverted sync input.
When open, this pin goes to the PECL
threshold voltage (IOVCC – 1.3V).
Only the Pin 7 SYNCH input with
SYNCL input open can be also
operated but complementary input is
recommended in order to realize
stable high-speed operation.
Pin
No.
Symbol I/O
Reference
voltage level
Equivalent circuit
Description
IOVCC
IOGND
14k
500
3
4
7
8
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