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参数资料
| 型号： | CXA3266Q |
| 元件分类： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 0.12 MHz, PQFP48 |
| 封装： | PLASTIC, QFP-48 |
| 文件页数： | 25/62页 |
| 文件大小： | 929K |
| 代理商： | CXA3266Q |
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CXA3266Q
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HOLD Timing
HOLD signal setup time (Ths) is a time from the rising edge of HOLD signal to the falling edge of DIVOUT. Or,
when SYNC POL = 1, it is a time from the falling edge of HOLD signal to the rising edge of SYNC ; when SYNC
POL = 0, it is the time from the falling edge of HOLD signal to the falling edge of SYNC.
HOLD signal hold time (Thh) is the time from the falling edge of DIVOUT to falling edge of HOLD signal. Or,
when SYNC POL = 1, it is the time from the rising edge of SYNC to the rising edge of HOLD signal ; when
SYNC POL = 0, it is the time from the falling edge of SYNC to the rising edge of HOLD signal.
When the HOLD input is held, the CLK frequency fluctuation can be calculated as follows.
C
V = Q = Ileak Thold
C
: Loop filter capacitance
V
: Voltage variation due to leakage current
Ileak
: Internal amplifier leakage current
Thold : Hold time
V = Ileak Thold/C
f = V KVCO = Ileak Thold/C KVCO
For example, assuming
f = 100MHz, Ileak = 1nA, Thold = 1ms, C = 0.068
F, and KVCO = 2π 75MHz, then ;
V = 1 × 10 – 9 1 × 10 – 3/(0.068 × 10 – 6) = 15 × 10 – 6 [V]
f = 1 × 10 – 9 1 × 10 – 3/(0.068 × 10 – 6) 75 × 106 = 1125 [Hz]
Thh
Ths
Thh
Ths
Thold
D/VOUT output
(TTL)
HOLD input
(TTL)
CLK output
SYNC input
(SYNC POL = 1)
SYNC input
(SYNC POL = 0)
The phase comparison output is held and fixed VCO output frequency is output.
VCO
I
SW
C
–Q
+Q
V
Ileak
f
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