DS3112+W (Maxim) PDF资料下载 Datasheet(101/133 页)

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型号：	DS3112+W
厂商：	Maxim Integrated Products
文件页数：	101/133页
文件大小：	0K
描述：	IC MUX T3/E3 3.3V 256-PBGA
产品培训模块：	Lead (SnPb) Finish for COTS Obsolescence Mitigation Program
标准包装：	40
控制器类型：	调帧器，多路复用器
接口：	并行/串行
电源电压：	3.135 V ~ 3.465 V
电流 - 电源：	150mA
工作温度：	0°C ~ 70°C
安装类型：	表面贴装
封装/外壳：	256-LBGA
供应商设备封装：	256-PBGA（27x27）
包装：	管件

DS3112

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DETAILED DESCRIPTION

The DS3112 TEMPE (T3 E3 MultiPlexEr) device can be used either as a multiplexer or a T3/E3 framer.

When the device is used as a multiplexer, it can be operated in one of three modes:

M13—Multiplex 28 T1 lines into a T3 data stream

E13—Multiplex 16 E1 lines into an E3 data stream

G.747—Multiplex 21 E1 lines into a T3 data stream

See Figure 1-1, Figure 1-2, and Figure 1-3 for block diagrams of these three modes. In each of the block

diagrams, the receive section is at the bottom and the transmit section is at the top. The receive path is

defined as incoming T3/E3 data and the transmit path is defined as outgoing T3/E3 data. When the device

is operated solely as a T3 or E3 framer, the multiplexer portion of the device is disabled and the raw

T3/E3 payload will be output at the FRD output and input at the FTD input. See Figure 1-1 and

Figure 1-2 for details.

In the receive path, raw T3/E3 data is clocked into the device (either in a bipolar or unipolar fashion) with

the HRCLK at the HRPOS and HRNEG inputs. The data is then framed by the T3/E3 framer and passed

through the two-step demultiplexing process to yield the resultant T1 and E1 data streams, which are

output at the LRCLK and LRDAT outputs. In the transmit path, the reverse occurs. The T1 and E1 data

streams are input to the device at the LTCLK and LTDAT inputs. The device will sample these inputs

and then multiplex the T1 and E1 data streams through a two-step multiplexing process to yield the

resultant T3 or E3 data stream. Then this data stream is passed through the T3/E3 formatter to have the

framing overhead added, and the final data stream to be transmitted is output at the HTPOS and HTNEG

outputs using the HTCLK output.

The DS3112 has been designed to meet all of the latest telecommunications standards. Section 1.1 lists all

of the applicable standards for the device.

The TEMPE device has a number of advanced features such as:

The ability to drop and insert up to two T1 or E1 ports

An on-board HDLC controller with 256-byte buffers

An on-board Bit Error Rate Tester (BERT)

Advanced diagnostics to create and detect many different types of errors

See Section 1.2 for a complete list of main features within the device.

相关代理商/技术参数	参数描述
DS3116MP000	制造商:Thomas & Betts 功能描述:MAXGARD - RR8F
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