- 您现在的位置：买卖IC网 > PDF目录11562 > DS3112+W (Maxim Integrated Products)IC MUX T3/E3 3.3V 256-PBGA PDF资料下载
参数资料
| 型号： | DS3112+W |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 97/133页 |
| 文件大小： | 0K |
| 描述： | IC MUX T3/E3 3.3V 256-PBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 控制器类型： | 调帧器，多路复用器 |
| 接口： | 并行/串行 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 150mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-PBGA（27x27） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页当前第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页
DS3112
66 of 133
Register Name:
T2E2SR2
Register Description:
T2/E2 Status Register 2
Register Address:
36h
Bit #
7
6
5
4
3
2
1
0
Name
IERAI
RAI7
RAI6
RAI5
RAI4
RAI3
RAI2
RAI1
Default
0
—
Bit #
15
14
13
12
11
10
9
8
Name
E2SOF4
E2SOF3
E2SOF2
E2SOF1
E2Sn4
E2Sn3
E2Sn2
E2Sn1
Default
—
Note: See Figure 6-2 for details on the signal flow for the status bits in the T2E2SR2 register. Bits that are underlined are read-only; all
other bits are read-write.
Bits 0 to 6: Remote Alarm Indication Signal Detected (RAIn when n = 1 to 7). This latched read-only alarm-
status bit will be set to a one each time the corresponding T2/E2/G.747 framer detects an incoming RAI alarm.
This bit will be cleared when read unless the RAI alarm still exists in that T2/E2/G.747 framer. A change in state of
the RAI in one or more of the T2/E2/G.747 framers can cause the T2E2SR2 status bit (in the MSR register) to be
set and a hardware interrupt to occur if the IERAI bit is set to a one and the T2E2SR2 bit in the Interrupt Mask for
MSR (IMSR) register is set to a one (Figure 6-2). The interrupt will be allowed to clear when this bit is read. The
RAI alarm criteria are described in Table 6-1, Table 6-2, and Table 6-3. In the E3 mode, RAI5 to RAI7 (bits 4 to 6)
are meaningless and should be ignored.
Bit 7: Interrupt Enable for Remote Alarm Indication Signal (IERAI). This bit should be set to one if the host
wishes to have RAI detection occurrences cause a hardware interrupt or the setting of the T2E2SR2 status bit in the
MSR register (Figure 6-2). The T2E2SR2 bit in the Interrupt Mask for the Master Status Register (IMSR) must
also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked
Bits 8 to 11: E2 Receive National Bit (E2Snn when n = 1 to 4). This read-only real-time status bit reports the
incoming E2 National Bit (Sn). It is loaded at the start of each E2 frame as the Sn bit is decoded. The host can use
the E2SOF status bit to determine when to read this bit. In the T3 and G.747 modes, this bit is meaningless and
should be ignored. This bit cannot cause an interrupt to occur.
Bits 12 to 15: E2 Receive Start Of Frame (E2SOFn where n = 1 to 4). This latched read-only event-status bit
will be set to a one on each E2 receive frame boundary. This bit will be cleared when read. The setting of this
status bit cannot cause an interrupt to occur.
Figure 6-2. T2E2SR2 Status Bit Flow
Alarm Latch
Change in State Detect
RAI1
(T2E2SR2
Bit 0)
Internal RAI
Signal from
T2/E2 Framer 1
Alarm Latch
Change in State Detect
Internal RAI
Signal from
T2/E2 Framer 2
Alarm Latch
Change in State Detect
Internal RAI
Signal from
T2 Framer 7
OR
Mask
IERAI
(T2E2SR2
Bit 7)
RAI2
(T2E2SR2
Bit 1)
RAI7
(T2E2SR2
Bit 6)
Mask
T2E2SR2
(IMSR Bit 6)
INT*
Hardware
Signal
T2E2SR2
Status Bit
(MSR Bit 6)
Event Latch
NOTE: ALL EVENT AND ALARM LATCHES ABOVE ARE CLEARED WHEN THE T2E2SR2 REGISTER IS READ.
相关PDF资料 |
PDF描述 |
|---|---|
| CONREVSMA007-R58 | CONN RP-SMA MALE END CRIMP RG-58 |
| DS26401NA2+ | IC OCTAL FRAMER T1/E1/J1 256BGA |
| VI-24L-IX-S | CONVERTER MOD DC/DC 28V 75W |
| DS26401+ | IC OCTAL FRAMER T1/E1/J1 256BGA |
| PIC16LF1938-E/SS | MCU 8BIT 16K FLASH 28SSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3116MP000 | 制造商:Thomas & Betts 功能描述:MAXGARD - RR8F |
| DS311X | 功能描述:KWIK-CHG DESIGNATION STRIPS DBL RoHS:是 类别:盒，外壳，支架 >> 插线台，插座面板 - 配件 系列:Kwik-Change® 标准包装:50 系列:- 附件类型:模拟插头，双 样式:耳机，0.173" 直径 包括:- |
| DS312 | 功能描述:插线板 DESIGN STRIP COVER RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48 |
| DS-312 | 制造商:MA-COM 制造商全称:M/A-COM Technology Solutions, Inc. 功能描述:Four-Way Power Divider, 10 - 500 MHz |
| DS312_09 | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-3E FPGA Family: Introduction and Ordering Information |
发布紧急采购，3分钟左右您将得到回复。