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参数资料
型号： DS3112+W
厂商： Maxim Integrated Products
文件页数： 41/133页
文件大小： 0K
描述： IC MUX T3/E3 3.3V 256-PBGA
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 40
控制器类型： 调帧器，多路复用器
接口： 并行/串行
电源电压： 3.135 V ~ 3.465 V
电流 - 电源： 150mA
工作温度： 0°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 256-LBGA
供应商设备封装： 256-PBGA（27x27）
包装： 管件
DS3112
15 of 133
PIN
NAME
TYPE
FUNCTION
D5
CRD(CDS)
I
CPU Bus Read Enable (CPU Bus Data Strobe)
A3
CWR
(CR/
W)
I
CPU Bus Write Enable (CPU Bus Read/Write Select)
A9
FRCLK
O
Receive Framer (T3 or E3) Clock Output
B9
FRD
O
Receive Framer (T3 or E3) Data Output
C9
FRDEN
O
Receive Framer (T3 or E3) Data Enable Output
C8
FRLOF
O
Receive Framer (T3 or E3) Loss Of Frame Output
B8
FRLOS
O
Receive Framer (T3 or E3) Loss Of Signal Output
A7
FRMECU
I
Receive Framer (T3 or E3) Manual Error Counter Update
A8
FRSOF
O
Receive Framer (T3 or E3) Start Of Frame Pulse
A10
FTCLK
I
Transmit Framer (T3 or E3) Clock Input
B10
FTD
I
Transmit Framer (T3 or E3) Data Input
C10
FTDEN
O
Transmit Framer (T3 or E3) Data Enable Output
C11
FTMEI
I
Transmit Framer (T3 or E3) Manual Error Insert Pulse
A11
FTSOF
I/O
Transmit Framer (T3 or E3) Start Of Frame Pulse
B6
G.747E
I
G.747 Mode Enable, 0 = Normal T3 Mode, 1 = G.747
Mode
A13
HRCLK
I
High-Speed (T3 or E3) Port Receive Clock Input
C12
HRNEG
I
High-Speed (T3 or E3) Port Receive Negative Data Input
B13
HRPOS
I
High-Speed (T3 or E3) Port Receive Positive or NRZ Data
Input
B14
HTCLK
O
High-Speed (T3 or E3) Port Transmit Clock Output
A14
HTNEG
O
High-Speed (T3 or E3) Port Transmit Negative Data
Output
C14
HTPOS
O
High-Speed (T3 or E3) Port Transmit Positive or NRZ Data
Output
D7
JTCLK
I
JTAG IEEE 1149.1 Test Serial Clock
B5
JTDI
I
JTAG IEEE 1149.1 Test Serial Data Input
A4
JTDO
O
JTAG IEEE 1149.1 Test Serial Data Output
A5
JTMS
I
JTAG IEEE 1149.1 Test Mode Select
C6
JTRST
I
JTAG IEEE 1149.1 Test Reset (Active Low)
G20
LRCCLK
I
Low-Speed (T1 or E1) Port Common Receive Clock Input
N2
LRCLK1
O
Low-Speed (T1 or E1) Receive Clock from Port 1
R1
LRCLK2
O
Low-Speed (T1 or E1) Receive Clock from Port 2
R3
LRCLK3
O
Low-Speed (T1 or E1) Receive Clock from Port 3
U2
LRCLK4
O
Low-Speed (T1 or E1) Receive Clock from Port 4
V2
LRCLK5
O
Low-Speed (T1 or E1) Receive Clock from Port 5
Y2
LRCLK6
O
Low-Speed (T1 or E1) Receive Clock from Port 6
Y3
LRCLK7
O
Low-Speed (T1 or E1) Receive Clock from Port 7
Y5
LRCLK8
O
Low-Speed (T1 or E1) Receive Clock from Port 8
Y6
LRCLK9
O
Low-Speed (T1 or E1) Receive Clock from Port 9
V8
LRCLK10
O
Low-Speed (T1 or E1) Receive Clock from Port 10
V9
LRCLK11
O
Low-Speed (T1 or E1) Receive Clock from Port 11
V10
LRCLK12
O
Low-Speed (T1 or E1) Receive Clock from Port 12
V11
LRCLK13
O
Low-Speed (T1 or E1) Receive Clock from Port 13
Y13
LRCLK14
O
Low-Speed (T1 or E1) Receive Clock from Port 14
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