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| 型号： | DS3112+W |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 62/133页 |
| 文件大小： | 0K |
| 描述： | IC MUX T3/E3 3.3V 256-PBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 控制器类型： | 调帧器，多路复用器 |
| 接口： | 并行/串行 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 150mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-PBGA（27x27） |
| 包装： | 管件 |
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DS3112
34 of 133
4.2 Master Configuration Registers Description
Register Name:
MC1
Register Description:
Master Configuration Register 1
Register Address:
02h
Bit #
7
6
5
4
3
2
1
0
Name
FTSOFC
LOTCMC
UNI
MECU
AECU
CBEN
UNCHEN
ZCSD
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
—
LLTM
DENMS
LRCCEN
LTCCEN
Default
—
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Zero Code Suppression Disable (ZCSD).
0 = enable the B3ZS and HDB3 encoders/decoders
1 = disable the B3ZS and HDB3 encoders/decoders
Bit 1: T3/E3 Unchannelized Mode Enable (UNCHEN). When this bit is set low, the M13/E13/G.747 multiplexer
is enabled and data at the FTD input is ignored. When this bit is set high, the M13/E13/G.747 multiplexer is
disabled and the LTDAT inputs are ignored. The table below displays which bits are not sampled at the FTD input
when UNCHEN = 1.
0 = enable the M13/E13/G.747 multiplexers and disable the FTD Input
1 = disable the M13/E13/G.747 multiplexers and enable the FTD Input
DS3112 MODE
BITS POSITIONS NOT
SAMPLED AT FTD
T3 M23 (C-Bit Parity
Disabled)
F/P/M/C/X
T3 C-Bit Parity
F/P/M/X
E3
FAS/Sn/RAI
Bit 2: T3 C-Bit Parity Mode Enable (CBEN). This bit is only active when the device is T3 mode. When this bit
is set low, C-Bit Parity is defeated and the C Bits are sourced from the M23 Multiplexer Block (Figure 1-1). This
bit should not be set low in the T3 unchannelized mode (UNCHEN = 1). When this bit is set high, C-Bit Parity
mode is enabled and the C bits are sourced from the T3 framer block (Figure 1-1 and Figure 1-3).
0 = disable C-Bit Parity mode (also known as the M23 Mode)
1 = enable C-Bit Parity mode
Bit 3: Automatic One-Second Error Counters Update Defeat (AECU). When this bit is set low, the device will
automatically update the T3/E3 performance error counters on an internally created one-second boundary. The host
will be notified of the update via the setting of the OST status bit in the Master Status Register. In this mode, the
host has a full one second period to retrieve the error information before if will be overwritten with the next update.
When this bit is set high, the device will defeat the automatic one-second update and enable a manual update mode.
In the manual update mode, the device relies on either the Framer Manual Error Counter Update (FRMECU)
hardware input signal or the MECU control bit to update the error counters. The FRMECU hardware input signal
and MECU control bit are logically ORed and hence a zero to one transition on either will initiate an error counter
update to occur. After either the FRMECU signal or MECU bit has toggled, the host must wait at least 100ns
before reading the error counters to allow the device time to complete the update.
0 = enable the automatic update mode and disable the manual update mode
1 = disable the automatic update mode and enable the manual update mode
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