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| 型号： | DS3112+W |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 81/133页 |
| 文件大小： | 0K |
| 描述： | IC MUX T3/E3 3.3V 256-PBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 控制器类型： | 调帧器，多路复用器 |
| 接口： | 并行/串行 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 150mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-PBGA（27x27） |
| 包装： | 管件 |
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DS3112
51 of 133
Register Name:
T3E3EIC
Register Description:
T3/E3 Error Insert Control Register
Register Address:
18h
Bit #
7
6
5
4
3
2
1
0
Name
MEIMS
FBEIC1
FBEIC0
FBEI
T3CPBEI
T3PBEI
EXZI
BPVI
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
—
Default
—
Bit 0: BiPolar Violation Insert (BPVI). A zero to one transition on this bit will cause a single BPV to be inserted
into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for the next
occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent
error to be inserted. Toggling this bit has no affect when the T3/E3 interface is in the Unipolar Mode (Section 4.2
for details about the Unipolar Mode). In the manual error insert mode (MEIMS = 1), errors will be inserted on each
toggle of the FTMEI input signal as long as this bit is set high. When this bit is set low, no errors will be inserted.
Bit 1: Excessive Zero Insert (EXZI). A zero to one transition on this bit will cause a single EXZ event to be
inserted into the transmit data stream. An EXZ event is defined as three or more consecutive zeros in the T3 mode
and four or more consecutive zeros in the E3 mode. Once this bit has been toggled from a zero to a one, the device
waits for the next possible B3ZS/HDB3 codeword insertion and it suppresses that codeword from being inserted
and hence this creates the EXZ event. This bit must be cleared and set again for a subsequent error to be inserted.
Toggling this bit has no affect when the T3/E3 interface is in the Unipolar Mode (Section 4.2 for details about the
Unipolar Mode). In the Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle of the
FTMEI input signal as long as this bit is set high. When this bit is set low, no errors will be inserted.
Bit 2: T3 Parity Bit Error Insert (T3PBEI). A zero to one transition on this bit will cause a single T3 parity error
event to be inserted into the transmit data stream. A T3 parity event is defined as flipping the proper polarity of
both the P bits in a T3 Frame. (See Section 14.5 for details about the P bits.) Once this bit has been toggled from a
zero to a one, the device waits for the next T3 frame to flip both P bits. This bit must be cleared and set again for a
subsequent error to be inserted. Toggling this bit has no affect when the device is operated in the E3 mode. In the
Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long
as this bit is set high. When this bit is set low, no errors will be inserted.
Bit 3: T3 C-Bit Parity Error Insert (T3CPBEI). A zero to one transition on this bit will cause a single T3 C-Bit
parity error event to be inserted into the transmit data stream. A T3 parity event is defined as flipping the proper
polarity of all three CP bits in a T3 Frame. (See Section 14.7 for details about the CP bits.) Once this bit has been
toggled from a zero to a one, the device waits for the next T3 frame to flip the three CP bits. This bit must be
cleared and set again for a subsequent error to be inserted. Toggling this bit has no affect when the T3 framer is not
operated in the C-Bit parity mode (See Section 14.7 for details about the C-Bit Parity mode.) or when the device is
operated in the E3 mode. In the Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle of
the FTMEI input signal as long as this bit is set high. When this bit is set low, no errors will be inserted.
Bit 4: Frame Bit Error Insert (FBEI). A zero to one transition on this bit will cause the transmit framer to
generate framing bit errors. The type of framing bit errors inserted is controlled by the FBEIC0 and FBEIC1 bits
(see discussion below). Once this bit has been toggled from a 0 to a 1, the device waits for the next possible
framing bit to insert the errors. This bit must be cleared and set again for a subsequent error to be inserted. In the
Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long
as this bit is set high. When this bit is set low, no errors will be inserted.
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