收藏本站
参数资料
型号： DS3112+W
厂商： Maxim Integrated Products
文件页数： 53/133页
文件大小： 0K
描述： IC MUX T3/E3 3.3V 256-PBGA
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 40
控制器类型： 调帧器，多路复用器
接口： 并行/串行
电源电压： 3.135 V ~ 3.465 V
电流 - 电源： 150mA
工作温度： 0°C ~ 70°C
安装类型： 表面贴装
封装/外壳： 256-LBGA
供应商设备封装： 256-PBGA（27x27）
包装： 管件
DS3112
26 of 133
Signal Name:
LRCCLK
Signal Description:
Low-Speed (T1 or E1) Receive Common Clock Input
Signal Type:
Input
If enabled via the LRCCEN control bit in Master Control Register 1 (Section 4.2), all 28 LRCLK or
16/21 LRCLK can be slaved to this common clock input. In T3 mode, LRCCLK would be a 1.544MHz
clock and in E3 mode, LRCCLK would be 2.048MHz. Use of this configuration is only possible in
applications where it can be guaranteed that all of the multiplexed T1 or E1 signals at the far end are
based on a common clock. If this signal is not used, then it should be tied low. This signal can be
internally inverted. This option is controlled via the LRCLKI control bit in Master Control Register 2
(Section 4.2).
2.6 Low-Speed (T1 or E1) Transmit Port Signal Description
Signal Name:
LTDAT1 to LTDAT28
Signal Description:
Low-Speed (T1 or E1) Transmit Serial Data Inputs
Signal Type:
Input
These input signals sample the serial data from the 28 T1 data streams or the 16/21 E1 data streams that
will be multiplexed into a single T3 or E3 data stream. Data can be clocked into the device either on
falling edges (normal clock mode) or rising edges (inverted clock mode) of the associated LTCLK. This
option is controlled via the LTCLKI control bit in Master Control Register 2 (Section 4.2). Also, the data
can be internally inverted before being multiplexed if enabled via the LTDATI control bit in Master
Control Register 2 (Section 4.2). When the device is in the E3 Mode, LTDAT17 to LTDAT28 are
ignored and should be tied low. When the device is in the G.747 Mode, LTDAT4, LTDAT8, LTDAT12,
LTDAT16, LTDAT20, LTDAT24, and LTDAT28 are ignored and should be tied low. When the
M13/E13 multiplexer is disabled, then these inputs are ignored and should be tied low.
Signal Name:
LTCLK1 to LTCLK28
Signal Description:
Low-Speed (T1 or E1) Transmit Serial Clock Inputs
Signal Type:
Input
These input signals clock data in from the 28 T1 data streams or from the 16/21 E1 data streams. The T1
or E1 serial data streams at the associated LTDAT signals can be clocked into the device either on falling
edges (normal clock mode) or rising edges (inverted clock mode) of LTCLK. This option is controlled via
the LTCLKI control bit in Master Control Register 2 (Section 4.2). When the device is in the E3 Mode,
LTCLK17 to LTCLK28 are meaningless and should be tied low. When the device is in the G.747 Mode,
LTCLK4, LTCLK8, LTCLK12, LTCLK16, LTCLK20, LTCLK24, and LTCLK28 are meaningless and
should be tied low. When the M13/E13 multiplexer is disabled, then these inputs are ignored and should
be tied low.
相关PDF资料
PDF描述
CONREVSMA007-R58 CONN RP-SMA MALE END CRIMP RG-58
DS26401NA2+ IC OCTAL FRAMER T1/E1/J1 256BGA
VI-24L-IX-S CONVERTER MOD DC/DC 28V 75W
DS26401+ IC OCTAL FRAMER T1/E1/J1 256BGA
PIC16LF1938-E/SS MCU 8BIT 16K FLASH 28SSOP
相关代理商/技术参数
参数描述
DS3116MP000 制造商:Thomas & Betts 功能描述:MAXGARD - RR8F
DS311X 功能描述:KWIK-CHG DESIGNATION STRIPS DBL RoHS:是 类别:盒，外壳，支架 >> 插线台，插座面板 - 配件 系列:Kwik-Change® 标准包装:50 系列:- 附件类型:模拟插头，双 样式:耳机，0.173" 直径 包括:-
DS312 功能描述:插线板 DESIGN STRIP COVER RoHS:否 制造商:Switchcraft 产品类型:Bantam (TT) 正规化: 高度/机架数量: 深度: 端接类型: 位置/触点数量:48
DS-312 制造商:MA-COM 制造商全称:M/A-COM Technology Solutions, Inc. 功能描述:Four-Way Power Divider, 10 - 500 MHz
DS312_09 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-3E FPGA Family: Introduction and Ordering Information
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*