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参数资料
| 型号： | DS3112+W |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 28/133页 |
| 文件大小： | 0K |
| 描述： | IC MUX T3/E3 3.3V 256-PBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 控制器类型： | 调帧器，多路复用器 |
| 接口： | 并行/串行 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 150mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-LBGA |
| 供应商设备封装： | 256-PBGA（27x27） |
| 包装： | 管件 |
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DS3112
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14.3
T2 Framing Structure
To understand the M12 function users must understand T2 framing. The T2 frame structure is made up of
four subframes called M subframes (
). The four M subframes are transmitted one after
another (...M1/M2/M3/M4/M1/M2...) to make up the complete T2 M frame data structure. Each M
subframe is made up of six blocks and each block is made up of 49 bits. The first bit of each block is
dedicated to overhead and the next 48 bits are the information bits where the T1 data will be placed for
transport. The definitions of the overhead bits are shown in Table 14-2 and the placements of the
overhead bits are shown in Figure 14-3.
Table 14-2. T2 Overhead Bit Assignments
OVERHEAD BIT
DESCRIPTION
M Bits
(M1/M2/M3)
The M bits provide the frame alignment pattern for the four M subframes. Like all
framing patterns, the M bits are fixed to a certain state (M1 = 0/M2 = 1/M3 = 1).
F Bits
(F1/F2)
The F bits provide the frame alignment pattern for the M frame. Like all framing
patterns, the F bits are fixed to a certain state (F1 = 0/F2 = 1).
C Bits
(C1/C2/C3)
In the M12 application, the C bits are used to indicate when stuffing occurs. If all three
C Bits within a subframe are set to 1, then stuffing has occurred in the stuff block of
that subframe. If all three C Bits are set to zero, then no stuffing has occurred. When
the three C bits are not equal, a majority vote is used to determine the true state. The
exception to this rule is when the C3 bit is the inverse of C1 and C2. When this occurs,
it indicates that the T1 signal should be looped back.
X Bit
The X bit is used as a Remote Alarm Indication (RAI). It will be set to a zero (X = 0)
when the T2 framer cannot synchronize. It will be set to a one (X = 1) otherwise.
14.4 M12 Multiplexing
The M12 function multiplexes four T1 lines into a single T2 line. Since there are four M subframes in the
T2 framing structure, it might be concluded that each M subframe supports one T1 line but this is not the
case. The four T1 lines are bit interleaved into the T2 framing structure. A bit from T1 line #1 is placed
immediately after the overhead bit, followed by a bit from T1 line #2, which is followed by a bit from T1
line #3, which is followed by a bit from T1 line #4, and then the process repeats. Since there are 48
information bits in each block, there are 12 bits from each T1 line in a block. The second and fourth T1
lines are logically inverted before the bit interleaving occurs.
The four T1 lines are mapped asynchronously into the T2 data stream. This implies that there is no T1
framing information passed to the T2 level. The four T1 lines can have independent timing sources and
they do not need to be timing locked to the T2 clock. To account for differences in timing, bit stuffing is
used. The last block of each M subframe is the stuff block (
). In each stuff block there is an
associated stuff bit (Figure 14-4) that will be either an information bit (if the three C bits are decoded to
be a zero) or a stuff bit (if the three C bits are decoded to be a one). As shown in Figure 14-4 the position
of the stuff bit varies depending on the M subframe. This is done to allow a stuffing opportunity to occur
on each T1 line in every T2 M frame. For example, if the C bits in M Subframe 2 were all set to one, then
the second bit after the F2 overhead bit in the last block would be a stuff bit instead of an information bit.
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