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参数资料
型号： MT48LC1M16A1S
厂商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件页数： 1/51页
文件大小： 1480K
代理商： MT48LC1M16A1S
16Mb: x16 SDRAM
16MSDRAMx16.p65 – Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
1
16Mb: x16
SDRAM
KEY TIMING PARAMETERS
SPEED
CLOCK
ACCESS TIME
CL = 3**
5.5ns
5.5ns
6ns
SETUP
HOLD
-6
-7
-8A
166 MHz
143 MHz
125 MHz
2ns
2ns
2ns
1ns
1ns
1ns
*Off-center parting line
**CL = CAS (READ) latency
1 Meg x 16
512K x 16 x 2 banks
2K or 4K
2K (A0-A10)
2 (BA)
256 (A0-A7)
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
SYNCHRONOUS
DRAM
MT48LC1M16A1 S - 512K x 16 x 2 banks
For the latest data sheet, please refer to the Micron Web
site:
www.micronsemi.com/datasheets/sdramds.html
PIN ASSIGNMENT (Top View )
50-Pin TSOP
FEATURES
PC100 functionality
Fully synchronous; all signals registered on
positive edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
1 Meg x 16 - 512K x 16 x 2 banks architecture with
11 row, 8 column addresses per bank
Programmable burst lengths: 1, 2, 4, 8 or full page
Auto Precharge Mode, includes CONCURRENT
AUTO PRECHARGE
Self Refresh and Adaptable Auto Refresh Modes
- 32ms, 2,048-cycle refresh or
- 64ms, 2,048-cycle refresh or
- 64ms, 4,096-cycle refresh
LVTTL-compatible inputs and outputs
Single +3.3V ±0.3V power supply
Supports CAS latency of 1, 2 and 3
OPTIONS
Configuration
1 Meg x 16 (512K x 16 x 2 banks)
MARKING
1M16A1
Plastic Package - OCPL*
50-pin TSOP (400 mil)
TG
Timing (Cycle Time)
6ns (166 MHz)
7ns (143 MHz)
8ns (125 MHz)
-6
-7
-8A
Refresh
2K or 4K with Self Refresh Mode at 64ms
S
Part Number Example:
MT48LC1M16A1TG-7S
Note:
The # symbol indicates signal is active LOW.
V
DD
DQ0
DQ1
VssQ
DQ2
DQ3
V
DD
Q
DQ4
DQ5
VssQ
DQ6
DQ7
V
DD
Q
DQML
WE#
CAS#
RAS#
CS#
BA
A10
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
VssQ
DQ13
DQ12
V
DD
Q
DQ11
DQ10
VssQ
DQ9
DQ8
V
DD
Q
NC
DQMH
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss
16MB (X16) SDRAM PART NUMBER
PART NUMBER
MT48LC1M16A1TG S
ARCHITECTURE
1 Meg x 16
GENERAL DESCRIPTION
The 16Mb SDRAM is a high-speed CMOS, dynamic
random-access memory containing 16,777,216 bits. It
is internally configured as a dual 512K x 16 DRAM with
a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the
512K x 16-bit banks is organized as 2,048 rows by 256
columns by 16 bits. Read and write accesses to the
SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
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相关代理商/技术参数
参数描述
MT48LC1M16A1-TG 制造商:Micron Technology Inc 功能描述:
MT48LC1M16A1TG6SE 制造商:MICRON 功能描述:New
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MT48LC1M16A1TG-7S 制造商:Mitel Networks Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP
MT48LC1M16A1TG-7SE 制造商:Micron Technology Inc 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP
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