- 您现在的位置：买卖IC网 > PDF目录385639 > MT48LC1M16A1S (Micron Technology, Inc.) SYNCHRONOUS DRAM PDF资料下载
参数资料
| 型号： | MT48LC1M16A1S |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件页数： | 13/51页 |
| 文件大小： | 1480K |
| 代理商： | MT48LC1M16A1S |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页当前第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页
16Mb: x16 SDRAM
16MSDRAMx16.p65
–
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
13
16Mb: x16
SDRAM
Upon completion of a burst, assuming no other
commands have been initiated, the DQs will go High-
Z. A full-page burst will continue until terminated (at
the end of the page it will wrap to column 0 and
continue).
Data from any READ burst may be truncated with
a subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a subsequent READ command. In either
case, a continuous flow of data can be maintained. The
first data element from the new burst follows either the
last element of a completed burst, or the last desired
data element of a longer burst which is being trun-
cated. The new READ command should be issued
x
cycles before the clock edge at which the last desired
REA DS
READ bursts are initiated with a READ command,
as shown in Figure 5.
The starting column and bank addresses are pro-
vided with the READ command and AUTO
PRECHARGE is either enabled or disabled for that burst
access. If AUTO PRECHARGE is enabled, the row being
accessed is precharged at the completion of the burst.
For the generic READ commands used in the following
illustrations, AUTO PRECHARGE is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available
following the CAS latency after the READ command.
Each subsequent data-out element will be valid by the
next positive clock edge. Figure 6 shows general timing
for each possible CAS latency setting.
Figure 5
READ Command
Figure 6
CAS Latency
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A0-A7
A10
BA
BANK 0
BANK 1
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A8-A9
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON
’
T CARE
UNDEFINED
CLK
DQ
T2
T1
T0
CAS Latency = 1
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
相关PDF资料 |
PDF描述 |
|---|---|
| MT48LC2M32LFFC | 512K x 32 x 4 banks 3.3v SDRAM(3.3V,512K x 32 x 4组同步动态RAM) |
| MT48LC4M16A2 | SYNCHRONOUS DRAM |
| MT48LC16M4A2 | RSD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 3.3V; Power: 1W; 1kVDC and 3kVDC Isolation Options; Approved for Medical Applications; Suitable for Automated Assembly; 8, 10 and 12 pin Pinning Style Options; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| MT48LC8M16A2 | SYNCHRONOUS DRAM |
| MT48V2M32LFFC | 512K x 32 x 4 banks 2.5V SDRAM(2.5V,512K x 32 x 4组同步动态RAM) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC1M16A1-TG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC1M16A1TG6SE | 制造商:MICRON 功能描述:New |
| MT48LC1M16A1TG-6SE | 制造商:Micron Technology Inc 功能描述:IC,SDRAM,2X512KX16,CMOS,TSOP,50PIN,PLASTIC |
| MT48LC1M16A1TG-7S | 制造商:Mitel Networks Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| MT48LC1M16A1TG-7SE | 制造商:Micron Technology Inc 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
发布紧急采购，3分钟左右您将得到回复。