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参数资料
| 型号： | MT48LC1M16A1S |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件页数： | 23/51页 |
| 文件大小： | 1480K |
| 代理商： | MT48LC1M16A1S |
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16Mb: x16 SDRAM
16MSDRAMx16.p65
–
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
23
16Mb: x16
SDRAM
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another
bank while an access command with AUTO
PRECHARGE enabled is executing is not allowed by
SDRAMs, unless the SDRAM supports CONCURRENT
AUTO PRECHARGE. Micron SDRAMs support CON-
CURRENT AUTO PRECHARGE. Four cases where
CONCURRENT AUTO PRECHARGE occurs are de-
fined below.
READ with AUTO PRECHARGE
1. Interrupted by a READ (with or without AUTO
PRECHARGE): A READ to bank m will interrupt a
READ on bank n, CAS latency later. The
PRECHARGE to bank n will begin when the READ
to bank m is registered (Figure 24).
2. Interrupted by a WRITE (with or without AUTO
PRECHARGE): A WRITE to bank m will interrupt a
READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank
n will begin when the WRITE to bank m is registered
(Figure 25).
CLK
DQ
D
OUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
READ - AP
BANK
n
NOP
NOP
NOP
NOP
D
OUT
a
+ 1
D
OUT
d
D
OUT
d
+ 1
NOP
T7
BANK
n
CAS Latency = 3 (BANK
m
)
BANK
m
ADDRESS
Idle
NOP
NOTE:
DQM is LOW.
BANK
n
,
COL
a
BANK
m
,
COL
d
READ - AP
BANK
m
Internal
States
t
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
READ with Burst of 4
Precharge
RP - BANK
n
tRP - BANK
m
CAS Latency = 3 (BANK
n
)
Figure 24
READ w ith AUTO PRECHARGE Interrupted by a READ
CLK
DQ
D
OUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
NOP
NOP
NOP
NOP
D
IN
d
+ 1
D
IN
d
D
IN
d
+ 2
D
IN
d
+ 3
NOP
T7
BANK
n
BANK
m
ADDRESS
Idle
NOP
DQM
NOTE:
1. DQM is HIGH at T2 to prevent D
OUT
-
a
+1 from contending with D
IN
-
d
at T4.
BANK
n
,
COL
a
BANK
m
,
COL
d
WRITE - AP
BANK
m
Internal
States
t
Page
Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
WRITE with Burst of 4
Write-Back
RP -
BANK
n
tWR -
BANK
m
CAS Latency = 3 (BANK
n
)
READ - AP
BANK
n
1
DON
’
T CARE
Figure 25
READ w ith AUTO PRECHARGE Interrupted by a WRITE
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC1M16A1-TG | 制造商:Micron Technology Inc 功能描述: |
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| MT48LC1M16A1TG-6SE | 制造商:Micron Technology Inc 功能描述:IC,SDRAM,2X512KX16,CMOS,TSOP,50PIN,PLASTIC |
| MT48LC1M16A1TG-7S | 制造商:Mitel Networks Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| MT48LC1M16A1TG-7SE | 制造商:Micron Technology Inc 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
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