- 您现在的位置：买卖IC网 > PDF目录385639 > MT48LC1M16A1S (Micron Technology, Inc.) SYNCHRONOUS DRAM PDF资料下载
参数资料
| 型号： | MT48LC1M16A1S |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件页数： | 21/51页 |
| 文件大小： | 1480K |
| 代理商： | MT48LC1M16A1S |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页
16Mb: x16 SDRAM
16MSDRAMx16.p65
–
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
21
16Mb: x16
SDRAM
Fixed-length or full-page WRITE bursts can be trun-
cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied
coincident with the BURST TERMINATE command
will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data
applied one clock previous to the BURST TERMINATE
command. This is shown in Figure 19, where data
n
is
the last desired data element of a longer burst.
Figure 21
POWER-DOWN
Figure 20
PRECHARGE Command
Figure 19
Terminating a WRITE Burst
CS#
WE#
CAS#
RAS#
CKE
CLK
A10
BA
BANK 1
HIGH
BANK 0 and 1
BANK 0 or 1
BANK 0
A0-A9
tRAS
tRC
tRCD
All banks idle
Input buffers gated off
Exit POWER-
DOWN mode
(
)
(
)
(
)
(
)
(
)
(
)
tCKS
< tCKS
COMMAND
NOP
ACTIVE
Enter POWER-
DOWN mode
NOP
CLK
CKE
(
)
(
)
(
)
(
)
DON
’
T CARE
CLK
DQ
DIN
n
(Data)
T2
T1
T0
COMMAND
ADDRESS
BURST
TERMINATE
WRITE
Next
Command
BANK,
COL
n
NOTE:
DQMs are low
(Address)
PRECHA RGE
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in
all banks (see Figure 20). The bank(s) will be available
for a subsequent row access some specified time (
t
RP)
after the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be
precharged, and in the case where only one bank is to
be precharged, input BA selects the bank. When all
banks are to be precharged, input BA is treated as
“Don’t Care.” Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
POWER-DOWN
POWER-DOWN occurs if CKE is registered LOW
coincident with a NOP or COMMAND INHIBIT, when
no accesses are in progress (see Figure 21). If POWER-
DOWN occurs when all banks are idle, this mode is
referred to as precharge power-down; if power-down
occurs when there is a row active in either bank, this
mode is referred to as active power-down. Entering
power-down deactivates the input and output buff-
ers, excluding CKE, for maximum power savings while
in standby. The device may not remain in the power-
down state longer than the refresh period (64ms) since
no refresh operations are performed in this mode.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting
t
CKS).
相关PDF资料 |
PDF描述 |
|---|---|
| MT48LC2M32LFFC | 512K x 32 x 4 banks 3.3v SDRAM(3.3V,512K x 32 x 4组同步动态RAM) |
| MT48LC4M16A2 | SYNCHRONOUS DRAM |
| MT48LC16M4A2 | RSD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 3.3V; Power: 1W; 1kVDC and 3kVDC Isolation Options; Approved for Medical Applications; Suitable for Automated Assembly; 8, 10 and 12 pin Pinning Style Options; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| MT48LC8M16A2 | SYNCHRONOUS DRAM |
| MT48V2M32LFFC | 512K x 32 x 4 banks 2.5V SDRAM(2.5V,512K x 32 x 4组同步动态RAM) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC1M16A1-TG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC1M16A1TG6SE | 制造商:MICRON 功能描述:New |
| MT48LC1M16A1TG-6SE | 制造商:Micron Technology Inc 功能描述:IC,SDRAM,2X512KX16,CMOS,TSOP,50PIN,PLASTIC |
| MT48LC1M16A1TG-7S | 制造商:Mitel Networks Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| MT48LC1M16A1TG-7SE | 制造商:Micron Technology Inc 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
发布紧急采购，3分钟左右您将得到回复。