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参数资料
| 型号： | MT48LC1M16A1S |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件页数： | 20/51页 |
| 文件大小： | 1480K |
| 代理商： | MT48LC1M16A1S |
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16Mb: x16 SDRAM
16MSDRAMx16.p65
–
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
20
16Mb: x16
SDRAM
issued
t
WR after the clock edge at which the last desired
input data element is registered. In addition, when
truncating a WRITE burst, the DQM signal must be
used to mask input data for the clock edge prior to, and
the clock edge coincident with, the PRECHARGE com-
mand. An example is shown in Figure 18. Data
n
+ 1 is
either the last of a burst of two or the last desired of a
longer burst. Following the PRECHARGE command, a
subsequent command to the same bank cannot be
issued until
t
RP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-
length burst with AUTO PRECHARGE. The disadvan-
tage of the PRECHARGE command is that it requires
that the command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
random write accesses within a page can be performed
as shown in Figure 16.
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
subsequent READ command. Once the READ com-
mand is registered, the data inputs will be ignored, and
WRITEs will not be executed. An example is shown in
Figure 17. Data
n
+ 1 is either the last of a burst of two,
or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-
lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that AUTO PRECHARGE
was not activated), and a full-page WRITE burst may
be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be
CLK
DQ
D
IN
n
T2
T1
T3
T0
COMMAND
ADDRESS
WRITE
BANK,
COL
n
D
IN
a
D
IN
x
D
IN
m
WRITE
WRITE
WRITE
BANK,
COL
a
BANK,
COL
x
BANK,
COL
m
NOTE:
Each WRITE command may be to any bank.
DQM is LOW.
Figure 16
Random WRITE Cycles
Figure 17
WRITE to READ
CLK
DQ
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
WRITE
BANK,
COL
n
D
IN
n
D
IN
n
+ 1
D
OUT
b
READ
NOP
NOP
BANK,
COL
b
NOP
D
OUT
b
+ 1
T4
T5
NOTE:
The WRITE command may be to any bank, and the READ command may
be to any bank. DQM is LOW. CAS latency = 2 for illustration.
Figure 18
WRITE to PRECHARGE
DQM
CLK
DQ
T2
T1
T4
T3
T0
COMMAND
ADDRESS
BCOL
a
,
n
T5
NOP
WRITE
PRECHARGE
NOP
NOP
DIN
n
DIN
n
+ 1
ACTIVE
tRP
DON
’
T CARE
BANK
(
a
or all)
t
WR
NOTE:
DQM could remain LOW in this example if the WRITE burst is a
fixed length of two. Future SDRAMs will require a
WR of at least
two clocks.
BROW
a
,
DQM
DQ
COMMAND
ADDRESS
BANK
a
,
COL
n
NOP
WRITE
PRECHARGE
NOP
D
IN
n
D
IN
n
+ 1
ACTIVE
tRP
BANK
(
a
or all)
t
WR
BANK
a
,
ROW
NOP
t
WR = 1 CLK (
t
CK
t
WR)
t
WR = 2 CLK (
t
CK <
t
WR)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC1M16A1-TG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC1M16A1TG6SE | 制造商:MICRON 功能描述:New |
| MT48LC1M16A1TG-6SE | 制造商:Micron Technology Inc 功能描述:IC,SDRAM,2X512KX16,CMOS,TSOP,50PIN,PLASTIC |
| MT48LC1M16A1TG-7S | 制造商:Mitel Networks Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| MT48LC1M16A1TG-7SE | 制造商:Micron Technology Inc 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
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