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| 型号： | MT48LC1M16A1S |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件页数： | 6/51页 |
| 文件大小： | 1480K |
| 代理商： | MT48LC1M16A1S |
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16Mb: x16 SDRAM
16MSDRAMx16.p65
–
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
6
16Mb: x16
SDRAM
FUNCTIONAL DESCRIPTION
In general, the SDRAM is a dual 512K x 16 DRAM
that operates at 3.3V and includes a synchronous
interface (all signals are registered on the positive edge
of the clock signal, CLK). Each of the 512K x 16-bit
banks is organized as 2,048 rows by 256 columns by 16
bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed (BA
selects the bank, A0-A10 select the row). The address
bits (A0-A7) registered coincident with the READ or
WRITE command are used to select the starting col-
umn location for the burst access.
Prior to normal operation, the SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register defi-
nition, command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation.
Once power is applied to V
DD
and V
DD
Q (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100μs delay
prior to applying any command other than a COM-
MAND INHIBIT or a NOP. Starting at some point
during this 100μs period and continuing at least
through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.
Once the 100μs delay has been satisfied, with at least
one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All banks must then be precharged, thereby
placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for Mode Register
programming. Because the Mode Register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific
mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst
mode, as shown in Figure 1. The Mode Register is
programmed via the LOAD MODE REGISTER com-
mand and will retain the stored information until it is
programmed again or the device loses power.
Mode Register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write burst
mode, and M10 and M11 are reserved for future use.
The Mode Register must be loaded when all banks
are idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating
either of these requirements will result in unspecified
operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable, as
shown in Figure 1. The burst length determines the
maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types, and a full-
page burst is available for the sequential type. The full-
page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown opera-
tion or incompatibility with future versions may result.
When a READ or WRITE command is issued, a
block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-A7 when the burst length is set to two,
by A2-A7 when the burst length is set to four and by A3-
A7 when the burst length is set to eight. The remaining
(least significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts
wrap within the page if the boundary is reached.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the
starting column address, as shown in Table 1.
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PDF描述 |
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| MT48LC2M32LFFC | 512K x 32 x 4 banks 3.3v SDRAM(3.3V,512K x 32 x 4组同步动态RAM) |
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| MT48LC16M4A2 | RSD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 3.3V; Power: 1W; 1kVDC and 3kVDC Isolation Options; Approved for Medical Applications; Suitable for Automated Assembly; 8, 10 and 12 pin Pinning Style Options; Optional Continuous Short Circuit Protected; Efficiency to 85% |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC1M16A1-TG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC1M16A1TG6SE | 制造商:MICRON 功能描述:New |
| MT48LC1M16A1TG-6SE | 制造商:Micron Technology Inc 功能描述:IC,SDRAM,2X512KX16,CMOS,TSOP,50PIN,PLASTIC |
| MT48LC1M16A1TG-7S | 制造商:Mitel Networks Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| MT48LC1M16A1TG-7SE | 制造商:Micron Technology Inc 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
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