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| 型号： | MT48LC1M16A1S |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件页数： | 10/51页 |
| 文件大小： | 1480K |
| 代理商： | MT48LC1M16A1S |
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16Mb: x16 SDRAM
16MSDRAMx16.p65
–
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
10
16Mb: x16
SDRAM
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM, re-
gardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations already
in progress are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-A10 and
BA. See Mode Register heading in Register Definition
section. The LOAD MODE REGISTER command can
only be issued when all banks are idle, and a subsequent
executable command cannot be issued until
t
MRD is
met.
A CTIV E
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA input selects the bank, and the address
provided on inputs A0-A10 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE com-
mand must be issued before opening a different row in
the same bank.
REA D
The READ command is used to initiate a burst read
access to an active row. The value on the BA input
selects the bank, and the address provided on inputs
A0-A7 selects the starting column location. The value
on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected,
the row being accessed will be precharged at the end of
the READ burst; if AUTO PRECHARGE is not selected,
the row will remain open for subsequent accesses. Read
data appears on the DQs, subject to the logic level on
the DQM inputs two clocks earlier. If a given DQM
signal was registered HIGH, the corresponding DQs
will be High-Z two clocks later; if the DQM signal was
registered LOW, the DQs will provide valid data.
WRITE
The WRITE command is used to initiate a burst
write access to an active row. The value on the BA input
selects the bank, and the address provided on inputs
A0-A7 selects the starting column location. The value
on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected,
the row being accessed will be precharged at the end of
the WRITE burst; if AUTO PRECHARGE is not selected,
the row will remain open for subsequent accesses.
Input data appearing on the DQs is written to the
memory array subject to the DQM input logic level
appearing coincident with the data. If a given DQM
signal is registered LOW, the corresponding data will be
written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that byte/column
location.
PRECHA RGE
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in
all banks. The bank(s) will be available for a subsequent
row access a specified time (
t
RP) after the PRECHARGE
command is issued. Input A10 determines whether one
or all banks are to be precharged, and in the case where
only one bank is to be precharged, input BA selects the
bank. Otherwise BA is treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE com-
mands being issued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, but without requiring an explicit command.
This is accomplished by using A10 to enable AUTO
PRECHARGE in conjunction with a specific READ or
WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is auto-
matically performed upon completion of the READ or
WRITE burst, except in the full-page burst mode, where
AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled
or disabled for each individual READ or WRITE com-
mand.
相关PDF资料 |
PDF描述 |
|---|---|
| MT48LC2M32LFFC | 512K x 32 x 4 banks 3.3v SDRAM(3.3V,512K x 32 x 4组同步动态RAM) |
| MT48LC4M16A2 | SYNCHRONOUS DRAM |
| MT48LC16M4A2 | RSD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 3.3V; Power: 1W; 1kVDC and 3kVDC Isolation Options; Approved for Medical Applications; Suitable for Automated Assembly; 8, 10 and 12 pin Pinning Style Options; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| MT48LC8M16A2 | SYNCHRONOUS DRAM |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC1M16A1-TG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC1M16A1TG6SE | 制造商:MICRON 功能描述:New |
| MT48LC1M16A1TG-6SE | 制造商:Micron Technology Inc 功能描述:IC,SDRAM,2X512KX16,CMOS,TSOP,50PIN,PLASTIC |
| MT48LC1M16A1TG-7S | 制造商:Mitel Networks Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| MT48LC1M16A1TG-7SE | 制造商:Micron Technology Inc 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
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