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参数资料
| 型号： | MT48LC1M16A1S |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件页数： | 14/51页 |
| 文件大小： | 1480K |
| 代理商： | MT48LC1M16A1S |
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16Mb: x16 SDRAM
16MSDRAMx16.p65
–
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
14
16Mb: x16
SDRAM
data element is valid, where
x
equals the CAS latency
minus one. This is shown in Figure 7 for READ latencies
of one, two and three; data element
n
+ 3 is either the
last of a burst of four or the last desired of a longer
burst. The 1 Meg x 16 SDRAM uses a pipelined architec-
Figure 7
Consecutive READ Bursts
ture and therefore does not require the 2
n
rule associ-
ated with a prefetch architecture. A READ command
can be initiated on any clock cycle following a previous
READ command. Full-speed, random read accesses
within a page can be performed as shown in Figure 8.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
BANK,
COL
n
DON
’
T CARE
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
X = 0 cycles
NOTE:
Each READ command may be to either bank. DQM is LOW.
CAS Latency = 1
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL
n
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
X = 1 cycle
CAS Latency = 2
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK,
COL
n
NOP
BANK,
COL
b
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
D
OUT
b
READ
NOP
T7
X = 2 cycles
CAS Latency = 3
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC1M16A1-TG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC1M16A1TG6SE | 制造商:MICRON 功能描述:New |
| MT48LC1M16A1TG-6SE | 制造商:Micron Technology Inc 功能描述:IC,SDRAM,2X512KX16,CMOS,TSOP,50PIN,PLASTIC |
| MT48LC1M16A1TG-7S | 制造商:Mitel Networks Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| MT48LC1M16A1TG-7SE | 制造商:Micron Technology Inc 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
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