参数资料
型号: MT48LC1M16A1S
厂商: Micron Technology, Inc.
英文描述: SYNCHRONOUS DRAM
中文描述: 同步DRAM
文件页数: 17/51页
文件大小: 1480K
代理商: MT48LC1M16A1S
16Mb: x16 SDRAM
16MSDRAMx16.p65
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
17
16Mb: x16
SDRAM
Figure 11
READ to PRECHARGE
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that AUTO PRECHARGE was not
activated) and a full-page burst may be truncated with
a PRECHARGE command to the same bank. The
PRECHARGE command should be issued
x
cycles be-
fore the clock edge at which the last desired data
element is valid, where
x
equals the CAS latency minus
one. This is shown in Figure 11 for each possible CAS
latency; data element
n
+ 3 is either the last of a burst of
four or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to
the same bank cannot be issued until
t
RP is met. Note
that part of the row precharge time is hidden during
the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-
length burst with AUTO PRECHARGE. The disadvan-
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
NOTE:
DQM is LOW.
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
CLK
DQ
D
OUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
NOP
NOP
NOP
BANK
a
,
COL
n
NOP
D
OUT
n
+ 1
D
OUT
n
+ 2
D
OUT
n
+ 3
PRECHARGE
ACTIVE
tRP
T7
BANK
a
,
ROW
BANK
(
a
or all)
DON
T CARE
X
= 0 cycles
CAS Latency = 1
X
= 1 cycle
CAS Latency = 2
CAS Latency = 3
BANK
a
,
COL
n
BANK
a
,
ROW
or all)
(
a
BANK
a
,
COL
n
BANK
a
,
ROW
BANK
(
a
or all)
X
= 2 cycles
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