参数资料
型号: MT48LC1M16A1S
厂商: Micron Technology, Inc.
英文描述: SYNCHRONOUS DRAM
中文描述: 同步DRAM
文件页数: 34/51页
文件大小: 1480K
代理商: MT48LC1M16A1S
16Mb: x16 SDRAM
16MSDRAMx16.p65
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
34
16Mb: x16
SDRAM
INITIALIZE AND LOAD MODE REGISTER
tCH
tCL
tCK
CKE
CLK
COMMAND
DQ
ADDRESS
BANK,
ROW
tRCAR
tMRD
tRC
AUTO REFRESH
AUTO REFRESH
Program Mode Register.
2, 3
tCMH
tCMS
Precharge
all banks.
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tRP
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tCKS
(
Power-up:
V
DD
and
CLK stable.
T=100μs
(MIN)
tAH
tAS
PRECHARGE
NOP
NOP
AUTO
REFRESH
NOP
LOAD MODE
REGISTER
ACTIVE
NOP
NOP
NOP
CODE
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AUTO
REFRESH
BANK(S)
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High-Z
tCKH
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()()
()()
DQM
1
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()()
DON
T CARE
UNDEFINED
()()
()()
T0
T1
Tn + 1
To + 1
Tp + 1
Tp + 2
Tp + 3
-6
-7
-8A
SYMBOL*
t
CKS
t
CMH
t
CMS
t
MRD
t
RC
t
RCAR
t
RP
MIN
2
1
2
2
60
66
18
MAX
MIN
2
1
2
2
70
70
21
MAX
MIN
2
1
2
2
80
80
24
MAX
UNITS
ns
ns
ns
t
CK
ns
ns
ns
TIMING PARAMETERS
-6
-7
-8A
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CK (1)
t
CKH
MIN
1
2
2.5
2.5
6
8
20
1
MAX
MIN
1
2
2.75
2.75
7
10
25
1
MAX
MIN
1
2
3
3
8
13
25
1
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
*CAS latency indicated in parentheses.
NOTE:
1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.
2. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
3. Outputs are guaranteed High-Z after command is issued.
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