参数资料
型号: MT48LC1M16A1S
厂商: Micron Technology, Inc.
英文描述: SYNCHRONOUS DRAM
中文描述: 同步DRAM
文件页数: 31/51页
文件大小: 1480K
代理商: MT48LC1M16A1S
16Mb: x16 SDRAM
16MSDRAMx16.p65
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
31
16Mb: x16
SDRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11) (0
°
C
T
A
+70
°
C)
AC CHARACTERISTICS
PARAMETER
Access time from CLK (pos. edge)
-6
-7
-8A
SYMBOL
t
AC
t
AC
t
AC
t
AH
t
AS
t
CH
t
CL
t
CK
t
CK
t
CK
t
CKH
t
CKS
t
CMH
t
CMS
t
DH
t
DS
t
HZ
t
HZ
t
HZ
t
LZ
t
OH
t
RAS
t
RC
t
RCAR
t
RCD
t
REF
t
RP
t
RRD
t
T
t
WR
MIN
MAX
5.5
8
18
MIN
MAX
5.5
8.5
22
MIN
MAX
6
9
22
UNITS NOTES
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
t
CK
ns
ns
CL = 3
CL = 2
CL = 1
22
22
Address hold time
Address setup time
CLK high level width
CLK low level width
Clock cycle time
1
2
1
2
1
2
3
3
8
13
25
1
2
1
2
1
2
2.5
2.5
6
8
20
1
2
1
2
1
2
2.75
2.75
7
10
25
1
2
1
2
1
2
CL = 3
CL = 2
CL = 1
23
22, 23
23
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
CL = 3
CL = 2
CL = 1
5.5
8
18
5.5
8.5
22
6
9
22
10
10
10
Data-out low-impedance time
Data-out hold time
ACTIVE to PRECHARGE command
AUTO REFRESH, ACTIVE command period
AUTO REFRESH period
ACTIVE to READ or WRITE delay
Refresh period - 2,048 or 4,096 rows
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time
WRITE recovery time
1
2
42
60
66
18
1
2
42
70
70
20
1
2.5
48
80
80
24
120,000
120,000
120,000
22
22
64
64
64
18
12
0.3
21
14
0.3
1 + 3ns
10
80
24
16
0.3
22
1.2
1.2
10
7
24
25
20
1 + 4ns
10
80
1 + 2ns
10
80
Exit SELF REFRESH to ACTIVE command
t
XSR
CAPACITANCE
PARAMETER
Input Capacitance: CLK
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQs
SYMBOL
C
I
1
C
I
2
C
IO
MIN
2.5
2.5
4.0
MAX
4.0
5.0
6.5
UNITS
pF
pF
pF
NOTES
2
2
2
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