- 您现在的位置：买卖IC网 > PDF目录385639 > MT48LC1M16A1S (Micron Technology, Inc.) SYNCHRONOUS DRAM PDF资料下载
参数资料
| 型号： | MT48LC1M16A1S |
| 厂商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件页数： | 9/51页 |
| 文件大小： | 1480K |
| 代理商： | MT48LC1M16A1S |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页
16Mb: x16 SDRAM
16MSDRAMx16.p65
–
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
9
16Mb: x16
SDRAM
TRUTH TABLE 1 – COMMANDS AND DQM OPERATION
(Notes: 1)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column and start READ burst)
WRITE (Select bank and column and
start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or
SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
CS# RAS# CAS# WE# DQM
H
X
X
L
H
H
L
L
H
L
H
L
L
H
L
ADDR
X
X
Bank/Row
DQs NOTES
X
X
X
X
X
H
H
H
L
X
X
X
3
4
4
L/H
8
Bank/Col
L/H
8
Bank/Col Valid
L
L
L
H
L
L
H
H
L
L
L
H
X
X
X
X
Active
X
X
Code
X
5
6, 7
L
–
–
L
–
–
L
–
–
L
–
–
X
L
H
Op-Code
–
–
X
2
8
8
Active
High-Z
following the Operation section; these tables provide
current state/next state information.
COMMANDS
Truth Table 1 provides a quick reference of available
commands. This is followed by a written description of
each command. Three additional Truth Tables appear
NOTE:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A10 and BA define the op-code written to the Mode Register.
3. A0-A10 provide row address, and BA determines which bank is made active.
4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables
the auto precharge feature; BA determines which bank is being read from or written to.
5. For A10 LOW, BA determines which bank is being precharged; for A10 HIGH, all banks are precharged and BA is a
“
Don
’
t Care.
”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are
“
Don
’
t Care
”
except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
相关PDF资料 |
PDF描述 |
|---|---|
| MT48LC2M32LFFC | 512K x 32 x 4 banks 3.3v SDRAM(3.3V,512K x 32 x 4组同步动态RAM) |
| MT48LC4M16A2 | SYNCHRONOUS DRAM |
| MT48LC16M4A2 | RSD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 3.3V; Power: 1W; 1kVDC and 3kVDC Isolation Options; Approved for Medical Applications; Suitable for Automated Assembly; 8, 10 and 12 pin Pinning Style Options; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| MT48LC8M16A2 | SYNCHRONOUS DRAM |
| MT48V2M32LFFC | 512K x 32 x 4 banks 2.5V SDRAM(2.5V,512K x 32 x 4组同步动态RAM) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT48LC1M16A1-TG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC1M16A1TG6SE | 制造商:MICRON 功能描述:New |
| MT48LC1M16A1TG-6SE | 制造商:Micron Technology Inc 功能描述:IC,SDRAM,2X512KX16,CMOS,TSOP,50PIN,PLASTIC |
| MT48LC1M16A1TG-7S | 制造商:Mitel Networks Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
| MT48LC1M16A1TG-7SE | 制造商:Micron Technology Inc 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
发布紧急采购，3分钟左右您将得到回复。