参数资料
型号: MT48LC1M16A1S
厂商: Micron Technology, Inc.
英文描述: SYNCHRONOUS DRAM
中文描述: 同步DRAM
文件页数: 11/51页
文件大小: 1480K
代理商: MT48LC1M16A1S
16Mb: x16 SDRAM
16MSDRAMx16.p65
Rev. 8/99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
11
16Mb: x16
SDRAM
AUTO PRECHARGE ensures that the PRECHARGE is
initiated at the earliest valid stage within a burst. The
user must not issue another command to the same bank
until the precharge time (
t
RP) is completed. This is
determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each
burst type in the Operation section of this data sheet.
BURST TERMINATE
The BURST TERMINATE command is used to trun-
cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated
as shown in the Operation section of this data sheet.
AUTO REFRESH
AUTO REFRESH is used during normal operation
of the SDRAM and is analogous to CAS#-BEFORE-
RAS# (CBR) REFRESH in conventional DRAMs. This
command is nonpersistent, so it must be issued each
time a refresh is required.
The addressing during an AUTO REFRESH com-
mand is generated by an internal refresh controller.
This means that the address lines are not used to
generate the refresh address, and are “Don’t Care”.
The 1 Meg x 16 SDRAM requires 2,048 AUTO
REFRESH cycles every 64ms (
t
REF) to ensure that each
row is refreshed. Distributed refresh would be achieved
by providing an AUTO REFRESH command once ev-
ery 31.25μs. Burst refresh could be accomplished by
issuing 2,048 AUTO REFRESH commands consecu-
tively at the minimum cycle rate of
t
RC.
To provide a 4K refresh scheme, the refresh rate
would be doubled. Thus, 2,048 AUTO-REFRESH com-
mands distributed every 15.625μs would allow the 1
Meg x 16 SDRAM to have a 4K refresh if required. Of
the three types of refreshs options, utilizing the 2,048
cycles every 64ms (31.25μs per refresh) provides the
maximum power savings.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
Once the SELF REFRESH command is registered, all the
inputs to the SDRAM become “Don’t Care,” with the
exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM
provides its own internal clocking, causing it to per-
form its own auto refresh cycles. The SDRAM must
remain in self refresh mode for a minimum period
equal to
t
RAS, and may remain in self refresh mode for
an indefinite period beyond that.
The procedure for exiting self refresh requires a
sequence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
t
XSR, because time is required for the completion of
any internal refresh in progress.
Upon exiting self refresh mode, AUTO REFRESH
commands may be issued every 15.625μs or less as both
SELF REFRESH and AUTO REFRESH utilize the row
refresh counter.
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