R8C/36T-A Group
13. DTC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 174 of 728
Aug 05, 2011
Figure 13.5
DTC Internal Operation Flowchart when DTC Activation Source is SSU/I2C bus
Receive Data Full (i = 0 to 3, 5, or 6) (j = 0 to 23)
Figure 13.6
DTC Internal Operation Flowchart when DTC Activation Source is SSU/I2C bus
Transmit Data Empty (i = 0 to 3, 5, or 6) (j = 0 to 23)
DTC activation source generation
NMIF = 1?
Read DTC vector
Read control data
Transfer data
(Reading the receive data register
sets the RDRF bit to 0)
(1)
Write back control data
CHNE = 1?
Branch 1
0 is written to the bit among bits DTCENi0 to DTCENi7 and an interrupt request is generated
when transfer is either of the following:
- Transfer causing the DTCCTj register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in
repeat mode
Yes
No
DTCENi0 to DTCENi7: Bits in DTCENi registers
RPTINT, CHNE: Bits in DTCCRj register
NMIF: Bit in DTCTL register
RDRF: Bit in SISR register
Branch 1
End
No
Yes
Read control data
Transfer data
(Reading the receive data register
sets the RDRF bit to 0)
(1)
Write back control data
CHNE = 1?
No
Write 0 to the bit among
DTCENi0 to DTCENi7
Generate an interrupt request
for the CPU
Transfer data
(Reading the receive data register
does not set the RDRF bit to 0)
Write back control data
CHNE = 1?
Yes
No
Interrupt handling
Read control data
Transfer data
(Reading the receive data register
does not set the RDRF bit to 0)
Write back control data
CHNE = 1?
Yes
No
Note:
1. When the DTC activation source is SSU/I
2C bus receive data full, the DTC does not set the RDRF bit in the SISR register to 0. Instead, reading
the receive data register during DTC data transfer sets the RDRF bit to 0.
DTC activation source generation
NMIF = 1?
Read DTC vector
Read control data
Transfer data
(writing the transmit data register
sets the TDRE bit to 0)
(1)
Write back control data
CHNE = 1?
Branch 1
0 is written to the bit among bits DTCENi0 to DTCENi7 when transfer is either of the following:
- Transfer causing the DTCCTj register value to change from 1 to 0 in normal mode
- Transfer causing the DTCCTj register value to change from 1 to 0 while the RPTINT bit is 1 in
repeat mode
Yes
No
DTCENi0 to DTCENi7: Bits in DTCENi registers
RPTINT, CHNE: Bits in DTCCRj register
NMIF: Bit in DTCTL register
TDRE: Bit in SISR register
Branch 1
End
No
Yes
Read control data
Transfer data
(writing the transmit data register
sets the TDRE bit to 0)
(1)
Write back control data
CHNE = 1?
No
Write 0 to the bit among
DTCENi0 to DTCENi7
Transfer data
(writing the transmit data register
sets the TDRE bit to 0)
(1)
Write back control data
CHNE = 1?
Yes
No
Read control data
Transfer data
(writing the transmit data register
sets the TDRE bit to 0)
(1)
Write back control data
CHNE = 1?
Yes
No
Note:
1. When the DTC activation source is SSU/I
2C bus transmit data empty, the DTC does not set the TDRE bit in the SISR register to 0. Instead, writing data
to the transmit data register during DTC data transfer sets the TDRE bit to 0.