R8C/36T-A Group
29. Usage Notes
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 706 of 728
Aug 05, 2011
29.11 Notes on Serial Interface (UART2)
29.11.1 Common to All Operating Modes
29.11.1.1 Register Access
The settings of the following registers can only be changed when the serial interface is disabled. Do not use
these settings when the serial interface is enabled.
U2MR register: CKDIR bit
U2C0 register: Bits CLK0 and CLK1
The settings of the following registers can only be changed while transmission/reception is stopped. Do not use
these settings during transmission/reception.
U2MR register: Bits SMD0 to SMD2, STPS, PRY, PRYE, and IOPOL
U2BRG register: Bits b0 to b7
U2C0 register: Bits CRS, CRD, NCH, CKPOL, and UFORM
U2C1 register: Bits U2IRS, U2RRM, U2LCH, and U2ERE
U2RXDF register: DF2EN bit
U2SMR5 register: MP bit
U2SMR3 register: Bits CKPH, NODC, and DL0 to DL2
U2SMR2 register: Bits IICM2, CSC, ALS, and STAC
U2SMR register: Bits IICM, ABC, ABSCS, and SSS
29.11.1.2 N-Channel-Open-Drain Control Bit
When UART2 is not used, set the following bits to 0.
U2C0 register: NCH bit
U2SMR3 register: NODC bit
29.11.2 Clock Synchronous Serial I/O Mode
29.11.2.1 Transmission/Reception
When the RTS function is used with an external clock, the RTS2 pin outputs a low level, which informs the
transmitting side that the MCU is ready for a receive operation. The RTS2 pin outputs a high level when a
receive operation starts. Therefore, the transmit timing and receive timing can be synchronized by connecting
the RTS2 pin to the CTS2 pin of the transmitting side. The RTS function is disabled when an internal clock is
selected.
29.11.2.2 Transmission
If an external clock is selected, the following conditions must be met while the external clock is held high when
the CKPOL bit in the U2C0 register is set to 0 (transmit data is output at the falling edge and receive data is
input at the rising edge of the transfer clock), or while the external clock is held low when the CKPOL bit is set
to 1 (transmit data is output at the rising edge and receive data is input at the falling edge of the transfer clock).
The TE bit in the U2C1 register = 1 (transmission enabled)
The TI bit in the U2C1 register = 0 (data present in the U2TB register)
If the CTS function is selected, input to the CTS2 pin = Low