R8C/36T-A Group
26. Flash Memory
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 633 of 728
Aug 05, 2011
26.3.4
Flash Memory Control Register 2 (FMR2)
Notes:
1. To set this bit to 1, first write 0 and then 1 immediately. Disable interrupts and DTC activation between writing 0
and writing 1.
2. To set the FMR21 bit to 0 (erase restart), set it when the FMR01 bit in the FMR0 register is 1 (CPU rewrite mode
enabled).
3. Set the FMR27 bit to 1 after setting either of the following:
Set the CPU clock to the low-speed on-chip oscillator clock divided by 4, 8, or 16.
Set the CPU clock to the XCIN clock divided by 1 (no division), 2, 4, or 8.
4. When the MCU exits wait mode or stop mode, if bits CM37 and CM36 (system clock select bits when exiting wait
mode or stop mode) in the CM3 register are 10b (high-speed on-chip oscillator clock selected) or 11b (XIN clock
selected), or if the CM35 bit in the CM3 register is 1 (no division), this bit is set to the value after reset.
When the FMR20 bit is set to 1 (enabled), the erase-suspend function is enabled.
When the FMR21 bit is set to 1, erase-suspend mode is entered. If the FMR22 bit is 1 (erase-suspend request
enabled by interrupt request), the FMR21 bit is automatically set to 1 (erase-suspend request) when an interrupt
request for the enabled interrupt is generated, and erase-suspend mode is entered. To restart auto-erasure, set the
FMR21 bit to 0 (erase restart).
[Condition for setting to 0]
Set to 0 by a program.
[Conditions for setting to 1]
When the FMR22 bit is 1 (erase-suspend request enabled by interrupt request) at the time an interrupt is
generated.
Set to 1 by a program.
Address 00256h
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
FMR20
Erase-suspend enable bit
0: Erase-suspend disabled
1: Erase-suspend enabled
R/W
b1
FMR21
Erase-suspend request bit
0: Erase restart
1: Erase-suspend request
R/W
b2
FMR22
Interrupt request suspend request enable bit
0: Erase-suspend request disabled by
interrupt request
1: Erase-suspend request enabled by
interrupt request
R/W
b3
—
Reserved
Set to 0.
R/W
b4
FMR24
Flash memory wait cycle control bit
0: Flash cycle
1: No flash cycle
R/W
b5
—
Reserved
Set to 0.
R/W
b6
—
Nothing is assigned. The write value must be 0. The read value is 0.
—
b7
FMR27
Low-current-consumption read mode enable bit
0: Low-current-consumption read mode
disabled
1: Low-current-consumption read mode
enabled
R/W