R8C/36T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 402 of 728
Aug 05, 2011
20.2.1
UART2 Transmit/Receive Mode Register (U2MR)
Notes:
1. In multiprocessor mode, set to 100b (UART mode transfer data length: 7 bits) or 101b (UART mode transfer data
length: 8 bits).
2. When setting bits SMD2 to SMD0 to 000b, set the TE bit in the U2C1 register to 0 (transmission disabled) and
the RE bit to 0 (reception disabled).
3. When using as master in SIO/I2C mode, set to 0 (internal clock). When using as slave in SIO/I2C mode, set to 1
(external clock).
4. Can only be selected in UART mode and multiprocessor communication mode. In other modes, set to 0 (one
stop bit).
5. Can only be selected in UART mode. In other modes, because the PRYE bit is set to 0 (no parity bit), the value
set to this bit is invalid.
6. Can only be selected in UART mode. In other modes, set to 0 (no parity bit).
If the PRYE bit is set to 1, the following operation occurs.
During transmission: Parity bit is added after transmit data.
During reception: Parity bit causes error checking to be performed.
7. Can only be set in UART mode. In other modes, set to 0 (not inverted). If the IOPOL bit is set to 1 (inverted), the
polarities of the transmit data and receive data are inverted.
(Start, stop, and parity bits are included in the inversion.)
20.2.2
UART2 Bit Rate Register (U2BRG)
Write to the U2BRG register using the MOV instruction while transmission and reception are stopped.
Set bits CLK0 and CLK1 in the U2C0 register before writing to the U2BRG register.
Address 000C0h
Bit
b7b6
b5b4b3
b2b1b0
Symbol
After Reset
0
000
0000
Bit
Symbol
Bit Name
Function
R/W
b0
SMD0
Serial I/O mode select bits
(1, 2)b2 b1 b0
0 0 0: Serial interface disabled
0 0 1: Clock synchronous serial I/O mode
01 0: I2C mode
1 0 0: UART mode, transfer data 7 bits long
1 0 1: UART mode, transfer data 8 bits long
1 1 0: UART mode, transfer data 9 bits long
Other than the above: Do not set.
R/W
b1
SMD1
R/W
b2
SMD2
R/W
b3
CKDIR
Internal/external clock select bit
(3)0: Internal clock
1: External clock
R/W
b4
STPS
Stop bit length select bit
(4)0: One stop bit
1: Two stop bits
R/W
b5
PRY
Odd/even parity select bit
(5)0: Odd parity
1: Even parity
R/W
b6
PRYE
0: Parity disabled
1: Parity enabled
R/W
b7
IOPOL
TXD and RXD I/O polarity switch bit
0: Not inverted
1: Inverted
R/W
Address 000C1h
Bit
b7b6
b5b4b3
b2b1b0
Symbol
————
———
—
After Reset
0
000
0000
Bit
Function
Setting Range
R/W
b7 to b0 If the setting value is n, U2BRG divides the count source by n + 1.
00h to FFh
W