![](http://datasheet.mmic.net.cn/120000/R5F2136CSDFP_datasheet_3573589/R5F2136CSDFP_111.png)
R8C/36T-A Group
8. Watchdog Timer
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 80 of 728
Aug 05, 2011
8.3.2
When Count Source Protection Mode is Disabled
When count source protection mode is disabled, the count source for the watchdog timer is the CPU clock or the
low-speed on-chip oscillator clock for the watchdog timer.
Notes:
1. The watchdog timer is initialized by writing 00h and then FFh to the WDTR register. The prescaler is initialized
after a reset. This results in discrepancies in the watchdog timer period due to the prescaler.
2. Only write to the WDTR register while the watchdog timer is counting.
3. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 at address 0FFFFh with a flash
programmer.
Table 8.3
Watchdog Timer Specifications when Count Source Protection Mode is Disabled
Item
Specification
Count source
CPU clock or low-speed on-chip oscillator clock for the watchdog timer (1/16)
Count operation
Decrement
Period
Prescaler division ratio (n) × Count value of the watchdog timer (m)
(1)Count source
n: 2, 16, or 128 (selected by bits WDTC6 and WDTC7 in the WDTC register)
However, when bits WDTC7 and WDTC6 are 11b (the count source is the low-speed on-
chip oscillator for the watchdog timer), n is 16.
m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register
Ex.: When the prescaler divides a CPU clock of 20 MHz by 16, and bits WDTUFS1 and
WDTUFS0 are 11b (3FFFh), the period is approx. 13.1 ms.
Watchdog timer
initialization conditions
Reset
00h and then FFh are written to the WDTR register
(2) Underflow
Count start conditions
The operation of the watchdog timer after a reset is selected by the WDTON bit
(3) in the
OFS register (address 0FFFFh).
When the WDTON bit is 1 (watchdog timer is stopped after reset)
The watchdog timer and the prescaler are stopped after a reset, and only start counting
when the WDTS register is written.
When the WDTON bit is 0 (watchdog timer automatically starts after reset)
The watchdog timer and the prescaler automatically start counting after a reset.
Count stop conditions
When the count source is obtained by dividing the CPU clock by 2, 16, or 128, if the MCU
enters wait mode or stop mode, count stops.
When the count source is obtained by dividing the watchdog timer low-speed on-chip
oscillator clock by 16, even if the MCU enters wait mode or stop mode, count does not
stop.
Operation at underflow When the RIS bit in the RISR register is 0
Watchdog timer interrupt
When the RIS bit in the RISR register is 1