R8C/36T-A Group
11. Interrupts
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 152 of 728
Aug 05, 2011
11.8
Timer RC Interrupt, Timer RE2 Interrupt, Synchronous Serial
Communication Unit/I2C bus Interface, and Flash Memory Interrupt
(Interrupts with Multiple Interrupt Request Sources)
The timer RC, timer RE2, synchronous serial communication unit/I2C bus interface, and flash memory interrupts
each have multiple interrupt request sources. An interrupt request is generated by the logical OR of several
interrupt request sources and is reflected in the IR bit in the corresponding interrupt control register. Therefore,
each of these peripheral functions has its own interrupt request source status register (status register) and interrupt
request source enable register (enable register) to control the generation of interrupt requests (change of the IR bit
As with other maskable interrupts, the timer RC, timer RE2, synchronous serial communication unit/I2C bus
interface, and flash memory interrupts are controlled by the combination of the IR bit, bits ILVL0 to ILVL2, and
IPL. However, since each interrupt source is generated by a combination of multiple interrupt request sources, the
following differences from other maskable interrupts apply:
When bits in the enable register are set to 1 and the corresponding bits in the status register are set to 1 (interrupt
enabled), the IR bit in the interrupt control register is set to 1 (interrupt requested).
When either bits in the status register or the corresponding bits in the enable register, or both are set to 0, the IR bit
is set to 0 (no interrupt requested).
That is, even if the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be
retained.
Also, if 0 is written to the IR bit, this bit is temporarily set to 0 (for five cycles of the CPU clock) and then set back
to 1.
Individual bits in the status register are not automatically set to 0 even if the interrupt is acknowledged.
The IR bit is also not automatically set to 0 when the interrupt is acknowledged.
Set individual bits in the status register to 0 in the interrupt routine. Refer to the status register figure for how to
set individual bits in the status register to 0.
When multiple bits in the enable register are set to 1 and other request sources are generated after the IR bit is set
to 1, the IR bit remains 1.
When multiple bits in the enable register are set to 1, use the status register to determine which request source
causes an interrupt.
Table 11.13
Registers Associated with Timer RC, Timer RE2, Synchronous Serial Communication
Unit/I2C bus Interface, and Flash Memory Interrupts
Peripheral Function
Name
Status Register of
Interrupt Request Source
Enable Register of
Interrupt Request Source
Interrupt Control
Register
Timer RC
TRCSR
TRCIER
TRCIC
Timer RE2
TREIFR
TREIER
TRE2IC
Synchronous serial
communication unit/I2C bus
interface
SISR_0
SIER_0
SSUIC_0/IICIC_0
Flash memory
RDYSTI
RDYSTIE
FMRDYIC
BSYAEI
BSYAEIE
CMDERIE