R8C/36T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 398 of 728
Aug 05, 2011
Note:
1. If an overrun error occurs, the receive data in the U2RB register will not be updated (the previous data will be
read).
Table 20.3
UART2 Specifications (3)
Item
Specification
Clock
asynchronous
serial I/O mode
(UART mode)
Selectable functions
LSB first/MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit
7 can be selected.
Serial data logic switching
This function inverts the logic of the transmit/receive data. The start and
stop bits are not inverted.
TXD and RXD I/O polarity switching
This function inverts the polarities of the TXD pin output and RXD pin
input. The logic levels of all I/O data are inverted.
RXD2 digital filter selection
The RXD2 input signal can be enabled or disabled.
Special mode 1
(I2C mode)
Pins used
SCL2: Transfer clock (master: output, slave: input)
SDA2: Transfer data (transmit: output, receive: input)
Noise filter
100 ns noise filter for CLK2 and RXD2 input
Transfer data format Transfer data length: 8 bits
Transfer clock
Master mode
The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n + 1))
fj = f1, f8, f32, or fC1
n = Value set in the U2BRG register (00h to FFh)
Slave mode
The CKDIR bit is set to 1 (external clock): Input from the SCL2 pin
Transmission start
conditions
To start transmission, the following requirements must be met:
(1) The TE bit in the U2C1 register is set to 1 (transmission enabled).
The TI bit in the U2C1 register is set to 0 (data present in the U2TB
register).
Reception start
conditions
To start reception, the following requirements must be met:
(1) The RE bit in the U2C1 register is set to 1 (reception enabled).
The TE bit in the U2C1 register is set to 1 (transmission enabled).
The TI bit in the U2C1 register is set to 0 (data present in the U2TB
register).
Interrupt request
generation timing
Start/stop condition detection, no acknowledgement detection, or
acknowledgement detection
Error detection
This error occurs if the next data reception starts before the U2RB
register is read and the 7th bit of the next data is received.
Selectable functions
Arbitration lost
The timing for updating the ABT bit in the U2RB register can be selected.
SDA2 digital delay
No digital delay or a delay of 2 to 8 cycles of the U2BRG count source
clock can be selected.
Clock phase setting
With or without clock delay can be selected.
Multiprocessor
communication
mode
Pins used
TXD2: Transmit data (output)
RXD2: Receive data (input)
CLK2: UART2 operating clock (input when external clock is selected)
Transfer data format Character bits (transfer data): 7 or 8 bits selectable
Multiprocessor bits: 1 bit
Start bits: 1 bit
Parity bit: No
Stop bits: 1 or 2 bits selectable
Selectable function
RXD2 digital filter selection
The RXD2 input signal can be enabled or disabled.
Specifications other than the above are identical to clock asynchronous serial I/O mode
specifications.