R8C/36T-A Group
18. Timer RE2
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 370 of 728
Aug 05, 2011
18.5
Interrupt Sources
The timer RE2 interrupt sources for are listed below:
Periodic interrupts (0.25 seconds, 0.5 seconds, 1 second, minutes, hours, a day, a month, a year)
Alarm interrupt
Compare match interrupt
Overflow interrupt
When using an interrupt, make necessary settings while the RUN bit in the TRECR register is 0 (count stops), and
then set the RUN bit to 1 (count starts).
[Real-time clock mode]
When an enabled periodic interrupt source is generated, the RTCF bit in the TREIFR register is set to 1 (interrupt
requested), and an interrupt request is generated.
When the alarm time and the counter match, the ALIF bit in the TREIFR register is set to 1 (interrupt requested).
When an alarm interrupt is enabled, an interrupt request is generated.
[Compare match timer mode]
When the compare match timer overflows, the OVIF bit in the TREIFR register is set to 1 (interrupt requested).
When the OVIE bit in the TRIER register is 1 (overflow interrupt enabled), an interrupt request is generated.
When the compare match timer is compared and matched, the CMIF bit in the TREIFR register is set to 1 (interrupt
requested). When the CMIE bit in the TREIER register is 1 (compare match interrupt enabled), an interrupt request
is generated.
Table 18.7
Timer RE2 Interrupt Sources
Source
Operating mode
Source Name
Interrupt Source
Interrupt Enable Bit
Real-time clock
period/overflow
Real-time clock
mode
Periodic interrupt
triggered every 0.25
seconds
0.25-second period
SEIE025
Periodic interrupt
triggered every 0.5
seconds
0.5-second period
SEIE05
Periodic interrupt
triggered every
second
The TRESEC register is
updated (one-second
period).
SEIE
Periodic interrupt
triggered every minute
The TREMIN register is
updated (one-minute period).
MNIE
Periodic interrupt
triggered every hour
The TREHR register is
updated (one-hour period).
HRIE
Periodic interrupt
triggered every day
The TREDY register is
updated (one-day period).
DYIE
Periodic interrupt
triggered every month
The TREMON register is
updated (one-month period).
MOIE
Periodic interrupt
triggered every year
The TREYR register is
updated (one-year period).
YRIE
Compare match
timer mode
Overflow interrupt
When the compare match
timer overflows.
OVIE
Alarm/compare match Real-time clock
mode
Alarm interrupt
When the alarm time set by
the alarm register (TREAMN,
TREAHR, or TREAWK
register only with enable bit
set as 1) and the counter
match.
ALIE
Compare match
timer mode
Compare match
interrupt
When the compare match
timer is compared and
matched.
CMIE