R8C/36T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 470 of 728
Aug 05, 2011
21.2.9.2
I2C bus Function
Notes:
1. Writing 1 to these bits has no effect. Each of these bits is set to 0 by writing 0 after reading it as 1.
2. Enabled in slave receive mode of I2C bus interface mode.
3. When two or more master devices attempt to occupy the bus at nearly the same time, if the I2C bus interface
monitors the SDA pin and the data which the I2C bus interface transmits is different, the ORER_AL bit is set to 1
indicating the bus is occupied by another master.
4. The NACKF bit is enabled when the ACKE bit in the SIER register is 1 (when the receive acknowledge bit is 1,
transfer is halted).
5. The RDRF bit is set to 0 when data is read from the SIRDR register. Do not clear this bit by writing 0 when not in
I2C bus interface mode or when not clearing the RDRF bit after DTC access.
6. Bits TEND and TDRE are set to 0 when data is written to the SITDR register.
Address 000EAh (SISR_0)
Bit
b7
b6b5
b4b3b2b1b0
Symbol
After Reset
00000000
Bit
Symbol
Bit Name
Function
R/W
b0
CE_ADZ
General call address
This flag is set to 1 when a general call address is
detected.
R/W
b1
AAS
Slave address recognition
This flag is set to 1 when the first frame immediately after
the start condition matches bits SVA0 to SVA6 in the
SIMR2 register in slave receive mode (slave address
detection, general call address detection).
R/W
b2
ORER_AL Arbitration lost flag/overrun
In I2C bus interface mode, this flag indicates that
arbitration is lost in master mode. This flag is set to 1
The internal SDA signal and SDA pin level do not match
at the rising edge of the SCL signal in master transmit
mode
The SDA pin is held high at start condition detection in
master transmit/receive mode
In clock synchronous serial mode, this bit indicates that
an overrun error has occurred. This flag is set to 1 when:
The last bit of the next data is received while the RDRF
bit is set to 1.
R/W
b3
STOP
Stop condition detection
This flag is set to 1 when a stop condition is detected
after the frame is transferred.
R/W
b4
NACKF
No acknowledge detection
This flag is set to 1 when no ACKnowledge is detected
from the receive device after transmission.
R/W
b5
RDRF
Receive data register full
This flag is set to 1 when receive data is transferred from
registers SISDR to SIRDR.
R/W
b6
TEND
In I2C bus interface mode, this flag is set to 1 at the rising
edge of the 9th clock cycle of the SCL signal while the
TDRE bit is 1.
In clock synchronous mode, this flag is set to 1 when the
last bit of the transmit frame is transmitted.
R/W
b7
TDRE
Transmit data empty flag
(1, 6) This flag is set to 1 when:
Data is transferred from registers SITDR to SISDR and
the SITDR register becomes empty.
The TRS bit in the SICR1 register is set to 1 (transmit
mode)
A start condition is generated (including retransmission)
Slave receive mode is changed to slave transmit mode
R/W