R8C/36T-A Group
21. Clock Synchronous Serial Interface
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 454 of 728
Aug 05, 2011
21.1.3
I2C bus Interface
The I2C bus interface is the circuit that performs serial communication based on the data transfer format of the
Philips I2C bus. This interface consists of a channel: I2C_0.
Table 21.4
I2C bus Interface Specifications
Item
Description
Communication modes
I2C bus interface mode
- Master or slave device can be selected.
- Continuous transmission and reception are supported (because the shift,
transmit, and receive registers are independent).
- Start/stop conditions are automatically generated in master mode.
- Automatic loading of the acknowledge bit during transmission.
- Bit synchronization and wait function are included. (In master mode, the state of
the SCL signal is monitored per bit and the timing is synchronized automatically.
If the transfer is not ready yet, the SCL signal is held low and the interface stands
by.)
- Direct drive of pins SCL and SDA (N-channel open-drain output) is supported.
Clock synchronous serial mode
Continuous transmission and reception are supported (because the shift, transmit,
and receive registers are independent).
I/O pins
SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
Transfer clocks
When the MST bit in the SICR1 register is 0 (slave mode)
External clock (input from the SCL pin)
When the MST bit in the SICR1 register is 1 (master mode)
Internal clock selected by bits CKS0 to CKS3 in the SICR1 register and bits
IICTCTWI and IICTCHALF in the IICCR register (output from the SCL pin)
Receive error detection
Overrun error detection (clock synchronous serial mode)
Indicates an overrun error has occurred during reception. When the last bit of the
next data is received while the RDRF bit in the SISR register is 1 (data present in
the SIRDR register), the ORER_AL bit in the SISR register is set to 1 (overrun
error).
Interrupt sources
I2C bus interface mode: 6 sources
Transmit data empty (including when slave address matches), transmit end,
receive data full (including when slave address matches), arbitration lost, NACK
detection, and stop condition detection
Clock synchronous serial mode: 4 sources
Transmit data empty, transmit end, receive data full, and overrun error
Selectable functions
I2C bus interface mode
The output level of the acknowledge signal during reception can be selected.
Clock synchronous serial mode
MSB first or LSB first can be selected as the data transfer direction.
SDA digital delay
The digital delay value of the SDA pin can be selected by bits SDADLY0 and
SDADLY1 in the IICCR register.