R8C/36T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 397 of 728
Aug 05, 2011
Notes:
1. If an overrun error occurs, the receive data in the U2RB register will not be updated (the previous data will be
read).
2. The framing error flag and the parity error flag are set to 1 when data is transferred from the UART2 receive
register to the U2RB register.
Table 20.2
UART2 Specifications (2)
Item
Specification
Clock
asynchronous
serial I/O mode
(UART mode)
Pins used
TXD2: Transmit data (output)
RXD2: Receive data (input)
CTS2: Transmit request signal (input)
RTS2: Receive request signal (output)
CLK2: Count source clock (input when external clock is selected)
Noise filter
10 ns noise filter for CLK2 and RXD2 input
Transfer data format
Character bits (transfer data): 7, 8, or 9 bits selectable
Start bits: 1 bit
Parity bit: Odd, even, or none selectable
Stop bits: 1 or 2 bits selectable
Transfer clock
The CKDIR bit in the U2MR register is set to 0 (internal clock):
fj/(16(n + 1))
fj = f1, f8, f32, or fC1
n = Value set in the U2BRG register: 00h to FFh
The CKDIR bit is set to 1 (external clock): fEXT/(16(n + 1))
fEXT: Input from CLK2 pin
n = Value set in the U2BRG register (00h to FFh)
Transmit/receive control CTS function, RTS function, or CTS/RTS function disabled selectable
Transmission start
conditions
To start transmission, the following requirements must be met:
The TE bit in the U2C1 register is set to 1 (transmission enabled).
The TI bit in the U2C1 register is set to 0 (data present in the U2TB
register).
If the CTS function is selected, input to the CTS2 pin is low.
Reception start
conditions
To start reception, the following requirements must be met:
The RE bit in the U2C1 register is set to 1 (reception enabled).
Start bit detection
Interrupt request
generation timing
For transmission, one of the following conditions can be selected.
-The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):
When data is transferred from the U2TB register to the UART2
transmit register (at start of transmission).
-The U2IRS bit in the U2C1 register is set to 1 (transmission
completed):
When data transmission from the UART2 transmit register is
completed.
For reception
When data is transferred from the UART2 receive register to the U2RB
register (at completion of reception).
Error detection
Overrun error (1)
This error occurs if the next data reception starts before the U2RB
register is read and the bit prior to the last stop bit in the next data is
received.
Framing error (2)
This error occurs when the set number of stop bits is not detected.
Parity error (2)
This error occurs if parity is enabled and the number of 1’s in the parity
and character bits does not match the set number of 1’s.
Error sum flag
This flag is set to 1 if an overrun, framing, or parity error occurs.