R8C/36T-A Group
11. Interrupts
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 142 of 728
Aug 05, 2011
11.4.4
Interrupt Sequence
The following describes the interrupt sequence performed from when an interrupt request is acknowledged until
the interrupt routine is executed.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority level after the instruction has completed. The CPU starts the interrupt sequence from the following
cycle. However, for the SMOVB, SMOVF, SSTR, and RMPA instructions, if an interrupt request is generated
while the instruction is being executed, the MCU suspends the instruction to start the interrupt sequence.
The interrupt sequence is performed as described below.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address
00000h. Then, the corresponding bit for the interrupt is set to 0 (no interrupt requeste
d).(1)(2) The FLG register is saved to a temporary register
(2) in the CPU immediately before the interrupt sequence
is entered.
(3) The I, D, and U flags in the FLG register are set as follows:
The I flag is 0 (interrupt disabled)
The D flag is 0 (single-step interrupt disabled)
The U flag is set to 0 (ISP selected).
However, the U flag does not change if an INT instruction for software interrupts numbered 32 to 63 is
executed.
(4) The CPU internal temporary register
(2) is saved on the stack.
(5) The PC is saved on the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The start address of the interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, instructions are executed from the start address of the interrupt
routine.
Notes:
Sources) for the IR bit operations of the timer RC interrupt, timer RE2 interrupt, synchronous serial
communication unit/I2C bus interface interrupt, and flash memory interrupt.
2. Temporary registers cannot be used by the user.
Figure 11.3
Time Required for Executing Interrupt Sequence
Note:
1. The length of the undefined state depends on the instruction queue buffer.
A read cycle occurs when the instruction queue buffer is ready to accept instructions .
CPU clock
Address bus
Data bus
RD
WR
Undefined
12
34567
8910
11
12
13
14
15
16
17
18
19
20
Address 00000h
Undefined
SP-2
SP-1
SP-4
SP-3
VEC
VEC+1
VEC+2
PC
Interrupt
information
Undefined
SP-2
contents
SP-1
contents
SP-4
contents SP-3 contents
VEC
contents
VEC+1 contents VEC+2 contents