R8C/36T-A Group
26. Flash Memory
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 628 of 728
Aug 05, 2011
26.3.2
Flash Memory Control Register 0 (FMR0)
Notes:
1. To set this bit to 1, first write 0 and then 1 immediately. Disable interrupts and DTC activation between writing 0
and writing 1.
2. Write to the FMSTP bit by a program transferred to the RAM. The FMSTP bit is enabled when the FMR01 bit is
set to 1 (CPU rewrite mode enabled). Do not set FMSTP bit to 1 (flash memory stops) when the FMR01 bit is 0
(CPU rewrite mode disabled). To set the FMSTP bit to 1 (flash memory stops), set it when the FST7 bit in the
FST register is 1 (ready).
3. The CMDRST bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled) and the FST7 bit in the
FST register is set to 0 (busy).
4. To set the FMR01 bit to 0 (CPU rewrite mode disabled), set it when the RDYSTI bit in the FST register is 0 (no
flash ready status interrupt requested) and the BSYAEI bit is 0 (no flash access error interrupt requested).
When the FMR01 bit is set to 1 (CPU rewrite mode enabled), software commands can be accepted.
When the FMR02 bit is set to 1 (EW1 mode), EW1 mode is selected.
This bit is used to initialize the flash memory control circuits, and also to reduce the amount of current
consumed by the flash memory. Access to the flash memory is disabled by setting the FMSTP bit to 1.
Write to the FMSTP bit by a program transferred to the RAM.
To reduce the power consumption further in high-speed on-chip oscillator mode, low-speed on-chip oscillator
mode (XIN clock stopped), and low-speed clock mode (XIN clock stopped), set the FMSTP bit to 1. Refer to
Address 00254h
Bit
b7b6
b5
b4
b3b2b1
b0
After Reset
0
000
00
Bit
Symbol
Bit Name
Function
R/W
b0
—
Reserved
Set to 0.
R/W
b1
FMR01
CPU rewrite mode select bit
0: CPU rewrite mode disabled
1: CPU rewrite mode enabled
R/W
b2
FMR02
EW1 mode select bit
0: EW0 mode
1: EW1 mode
R/W
b3
FMSTP
Flash memory stop bit
0: Flash memory operates
1: Flash memory stops
(Low-power consumption state, flash memory
initialization)
R/W
b4
CMDRST
Erase/write sequence reset bit
When the CMDRST bit is set to 1, the
erase/write sequence is reset and
erasure/writing can be forcibly stopped.
The read value is 0.
R/W
b5
CMDERIE Erase/write error interrupt enable bit
0: Erase/write error interrupt disabled
1: Erase/write error interrupt enabled
R/W
b6
BSYAEIE
Flash access error interrupt enable bit 0: Flash access error interrupt disabled
1: Flash access error interrupt enabled
R/W
b7
RDYSTIE
Flash ready status interrupt enable bit 0: Flash ready status interrupt disabled
1: Flash ready status interrupt enabled
R/W