R8C/36T-A Group
15. Timer RJ
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 240 of 728
Aug 05, 2011
15.5
Notes on Timer RJ
(1) Timer RJ stops counting after a reset. Start the count only after setting the values of the registers associated
timer RJ.
(2) There are the following restrictions on register access while the count is stopped, depending on the timer
mode:
Event count mode
After 1 (count starts) is written to the TSTART bit in the TRJCR register while the count is stopped, the
TCSTF bit in the TRJCR register remains 0 (count stops) for two cycles of the CPU clock. Do not access the
registers associated with timer RJ (1) other than the TCSTF bit until this bit is set to 1 (count in progress).
After the TCSTF bit is set to 1, the count is started from the first active edge of the count source.
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for two
cycles of the CPU clock. When the TCSTF bit is set to 0, the count is stopped. Do not access the registers
associated with timer RJ (1) other than the TRJ register until the TCSTF bit is set to 0. Writing to the TRJ
register has no effect until the TRJIO pin is set to the inactive level (low level when the TEDGSEL bit in the
TRJIOC register is 0 and high level when this bit is 1). To change the TRJ register in this case, use the
following procedure:
1. Write 0 to the TSTART bit to stop the count.
2. Wait until the TCSTF bit is set to 0.
3. Set bits TIPF1 and TIPF0 in the TRJIOC register to 00b (no filter). This setting is not necessary when no
digital filter is used.
4. Write 1 and then write 0 to the TEDGSEL bit.
5. Set the TEDGSEL bit to the previous value (value before step 4).
6. Set bits TIPF1 and TIPF0 to the previous value (value before step 3).
7. Access the TRJ register.
Modes other than event count mode
After 1 (count starts) is written to the TSTART bit while the count is stopped, the TCSTF bit remains 0 (count
stops) for three cycles of the count source. Do not access the registers associated with timer RJ (1) other than
the TCSTF bit until this bit is set to 1 (count in progress). After the TCSTF bit is set to 1, the count is started at
the first active edge of the counter source.
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for three
cycles of the count source. When the TCSTF bit is set to 0, the count is stopped. Do not access the registers
associated with timer RJ (1) other than the TCSTF bit until this bit is set to 0.
Note:
1. Registers associated with timer RJ: TRJ, TRJCR, TRJIOC, and TRJMR
(3) In event counter mode, set the TSTART bit in the TRJCR register to 1 (count starts), and then input an external
event after the TCSTF bit is set to 1.
Number of counted events = initial value in the counter – value in the counter on completion of the valid event
+ 1
(4) In pulse width/pulse period measurement modes, bits TEDGF and TUNDF in the TRJCR register used are set
to 0 by writing 0 by a program, but remain unchanged even if 1 is written to these bits. If a bit manipulation
instruction is used to set the TRJCR register, bits TEDGF and TUNDF may be erroneously set to 0 depending
on the timing, even when the TEDGF bit is set to 1 (active edge received) and the TUNDF bit is set to 1
(underflow) during execution of the instruction.
In order to avoid this, set bits TEDGF and TUNDF to 1 using the MOV instruction.
(5) The period for pulse period measurement mode is calculated as follows:
The period data of the input pulse = (initial value set in the counter – value read from the read-out buffer) + 1
(6) Insert two NOP instructions between writing to and reading from registers associated with the TRJ counter
while the counter is stopped.
(7) When the TSTART bit in the TRJCR register is 1 (count starts) or the TCSTF bit is 1 (count in progress),
allow at least three cycles of the count source clock between writes when writing to the TRJ register
successively.
(8) When the operating mode is switched, the values of bits TEDGF and TUNDF are undefined. Write 0 (no
active edge received) to the TEDGF bit and 0 (no underflow) to the TUNDF bit before starting timer RJ count.
(9) When bits TSTART and TCSTF are 0 (count stops), switch to module standby mode. For details on switching
to module standby mode, refer to 10.2.9 Module Standby Control Register 2 (MSTCR2).