R8C/36T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 434 of 728
Aug 05, 2011
20.3.3.8
SCL Synchronization Function
It may happen that another device holds SCL output low and forces the clock sent from the master into a wait
state. The SCL synchronization function of UART2 automatically enters a wait state when held low by another
device, and cancels the wait state when released from low output. This function is enabled by setting the CSC
bit to 1, and disabled by setting it to 0. This function should only be used when the MCU is the master.
FigureFigure 20.17
Timing of Clock Synchronization Function
20.3.3.9
SCL2 Pin Output Function
(1) SCL2 Pin Low Output Hold Function 1
The I2C bus sends a specified slave address in the first byte after a start condition is detected. In the first
byte, the slave needs to compare the receive data in the first 7 bits of the clock sent from another master
with its own address, and generate (or not generate) an acknowledge in synchronization with the 9th bit of
the clock. SCL2 pin low output hold function 1 of UART2 was created for this process.
By using this function, a low level is output to the SCL2 pin in synchronization with the SCL2 of the 9th
bit going low after the first 8 bits of data are received. This forces the master into a wait state. The function
can also generate/not generate an acknowledge after the address comparison processing by software is
completed.
This function is enabled by setting the SWC bit to 1, and disabled by setting it to 0. After the SCL2 pin has
been driven low by this function, it can be released from low level by setting the SWC bit to 0. Note that
when this function is used for address comparison, the contents of the buffer register are read out before
the rising of the clock corresponding to the last bit. This means that the bit positions of the received data
Transmit data is written
The clock synchronization function operates during this period.
SCL2
Internal baud
rate clock
Effective range of clock synchronization function
The UART2 internal SCL goes high, but
because the SCL2 pin is low, low is retained.
Although the UART2 internal SCL was
originally outputting a high level, a low level
is output and the low-level count operation
starts when the SCL2 pin falls.
Even if the UART2 internal SCL goes high, because
the SCL2 pin is low, the high-level count operation is
stopped during this period.
Internal SCL
Operation of clock synchronization function
SCL2 pin
UART2
clock
12
345
67
89