R8C/36T-A Group
29. Usage Notes
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0241EJ0010 Rev.0.10
Page 709 of 728
Aug 05, 2011
29.12 Notes on Clock Synchronous Serial Interface
29.12.1 Notes on Synchronous Serial Communication Unit
To use the synchronous serial communication unit, set the IICSEL bit in the IICCR register to 0 (SSU function
selected).
29.12.2 Notes on I2C bus Interface
To use the I2C bus interface, set the IICSEL bit in the IICCR register to 1 (I2C bus function selected).
(1) Do not use the I2C interface with settings that do not comply with the I2C specification.
(2) Communication using “Hs-MODE” cannot be performed. The maximum transfer rate is [a maximum of
400 kHz] in “FAST-MODE”.
(3) The low-level period of the SCL signal is [a minimum of 1.3
s] in “FAST-MODE”. Since the high-
level/low-level width of the duty cycle for this module is 50%/50%, this value is not reached during
operation at 400 kHz. Therefore, the maximum transfer rate is 2.6
s for the SCL period (maximum
transfer frequency is 384.6 kHz).
(4) There must be a delay of [a minimum of 300 ns] for the SDA pin to change at the rising edge of the SCL
signal. The SDA digital delay for this module must be at least 3 x f1 cycles, care must be taken when the
reference clock f1 is set to 11 MHz or above. Set bits SDADLY1 and SDADLY0 to 01b or more.
(5) There is no compatibility with the CBUS.
(6) 10-bit addressing cannot used.
(7) When a start condition is detected while data is transmitted in slave transmit mode, any address following
that condition cannot be received and the operation is stopped. Initialize the module according to the flow
for resetting the control block.
(8) Do not set 1111XXXb and 0000XXXb as slave addresses.
(9) When starting communication by the master after a stop condition is detected, always clear the STOP bit in
the SISR register to 0.
29.12.3 ICE Bit in SICR1 Register and SIRST Bit in SICR2 Register
While the I2C bus interface is operating, when 0 is written to the ICE bit or 1 is written to the SIRST bit in the
SICR2 register, the values of the BBSY bit in the SICR2 register and the STOP bit in the SISR register may be
undefined.
29.12.3.1 Conditions when Values of Bits are Undefined
When this module occupies the I2C bus in master mode of the I2C bus interface.
While this module transmits data or an acknowledge in slave mode of the I2C bus interface.
29.12.3.2 Countermeasures
When a start condition (falling of SDA when SCL is high) is input, the BBSY bit is set to 1.
When a stop condition (rising of SDA when SCL is high) is input, the BBSY bit is set to 0.
In master transmit mode, while SCL and SDA are both high, when 1 is written to the BBSY bit, 0 is written to
the SCP bit, and a start condition (falling of SDA when SCL is high) is output, the BBSY bit is set to 1.
In master transmit mode or master receive mode, while SDA is low and this module is the only device that
pulls SCL low, when 0 is written to the BBSY bit, 0 is written to the SCP bit in the SICR2 register, and a stop
condition (rising of SDA when SCL is high) is output, the BBSY bit is set to 1.
When 1 is written to the MS bit in the SAR register, the BBSY bit is set to 0.