R8C/36T-A Group
10. Power Control
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 126 of 728
Aug 05, 2011
10.7
Notes on Power Control
10.7.1
Stop Mode
To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) before setting the
CM10 bit in the CM1 register to 1 (stop mode). The 4 bytes of instruction data following the instruction that
sets the CM10 bit to 1 (stop mode) are prefetched from the instruction queue and then the program stops.
Insert at least four NOP instructions following the JMP.B instruction immediately after the instruction that sets
the CM10 bit to 1.
Program example for entering stop mode
BCLR
1, FMR0
; CPU rewrite mode disabled
BSET
0, PRCR
; Protection disabled
FSET
I
; Interrupt enabled
BSET
0, CM1
; Stop mode
JMP.B
LABEL_001
LABEL_001:
NOP
10.7.2
Wait Mode
To enter wait mode by setting the CM30 bit in the CM3 register to 1, set the FMR01 bit to 0 (CPU rewrite mode
disabled) before setting the CM30 bit to 1.
To enter wait mode with the WAIT instruction, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode
disabled) before executing the WAIT instruction. The 4 bytes of instruction data following the instruction that
sets the CM30 bit to 1 (MCU enters wait mode) or the WAIT instruction are prefetched from the instruction
queue and then the program stops. Insert at least four NOP instructions after the instruction that sets the CM30
bit to 1 (MCU enters wait mode) or the WAIT instruction.
Program example for executing the WAIT instruction
BCLR
1, FMR0
; CPU rewrite mode disabled
FSET
I
; Interrupt enabled
WAIT
; Wait mode
NOP
Program example for executing the instruction that sets the CM30 bit to 1
BCLR
1, FMR0
; CPU rewrite mode disabled
BSET
0, PRCR
; Writing to CM3 register enabled
FCLR
I
; Interrupt enabled
BSET
0, CM3
; Wait mode
NOP
BCLR
0, PRCR
; Writing to CM3 register disabled
FSET
I
; Interrupt enabled
To perform DTC transfers using DTC activation by the TSCU function during wait mode, the following settings
are required:
Set the FMR11 bit in flash memory control register 1 = 1 (flash memory operation during wait mode enabled)
Set the FMR27 bit in flash memory control register 2 = 1 (low-current-consumption read mode enabled)
Set the SVC0 bit in the STBY VDC power register = 0 (transition to low-power-consumption mode disabled)