R8C/36T-A Group
19. Serial Interface (UART0)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 387 of 728
Aug 05, 2011
19.3.2
Clock Asynchronous Serial I/O (UART) Mode
In clock asynchronous serial I/O mode, transmission and reception are performed at an arbitrary bit rate and in
an arbitrary format.
Notes:
1. If an overrun error occurs, the receive data (b0 to b8) in the U0RB register is undefined.
2. The framing error flag and the parity error flag are set to 1 when data is transferred from the UART0 receive
register to the U0RB register.
Table 19.6
Clock Asynchronous Serial I/O Mode Specifications
Item
Specification
Transfer data format
Character bits (transfer data): 7, 8 or 9 bits selectable
Start bit: 1 bit
Parity bit: Odd, even, or none selectable
Stop bits: 1 or 2 bits selectable
Transfer clock
The CKDIR bit in the U0MR register is 0 (internal clock): fj/16 (n + 1)
fj = f1, f8, f32, or fC1
n = Value set in the U0BRG register (00h to FFh)
The CKDIR bit in the U0MR register is 1 (external clock): fEXT/16 (n + 1)
fEXT (input from the CLK pin)
n = Value set in the U0BRG register (00h to FFh)
Transmission start
conditions
To start transmission, the following requirements must be met:
The TE bit in the U0C1 register is set to 1 (transmission enabled).
The TI bit in the U0C1 register is set to 0 (data present in the U0TB register).
Reception start
conditions
To start reception, the following requirements must be met:
The RE bit in the U0C1 register is set to 1 (reception enabled).
Start bit detection
Interrupt request
generation timing
For transmission, one of the following can be selected.
- The U0IRS bit in the U0C1 register is set to 0 (transmit buffer empty):
When data is transferred from the U0TB register to the UART0 transmit register (at
start of transmission).
- The U0IRS bit in the U0C1 register is set to 1 (transmission completed):
When data transmission from the UART0 transmit register is completed.
For reception
When data is transferred from the UART0 receive register to the U0RB register (at
completion of reception).
Error detection
This error occurs if the next data reception starts before the U0RB register is read and
the bit prior to the last stop bit in the next data is received.
This error occurs when the set number of stop bits is not detected.
This error occurs when parity is enabled, and the number of 1’s in the parity and
character bits do not match the set number of 1’s.
Error sum flag
This flag is set to 1 if an overrun, framing, or parity error occurs.