R8C/36T-A Group
13. DTC
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 178 of 728
Aug 05, 2011
13.3.6
Chain Transfers
When the CHNE bit in registers DTCCR0 to DTCCR22 are 1 (chain transfers enabled), multiple data transfers
When the DTC is activated, one control data is selected according to the data read from the DTC vector address
corresponding to the activation source, and the selected control data is read from the DTC control data area.
When the CHNE bit for the control data is 1, the next control data immediately following the current control
data is read and transferred after the current transfer is completed. This operation is repeated until the data
transfer with the control data for which the CHNE bit is 0 (chain transfers disabled) is completed.
Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).
Data transfers corresponding to each activation source can be set to either normal mode or repeat mode.
Figure 13.10
Flow of Chain Transfers
13.3.7
Interrupt Sources
When the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed in normal
mode, and when the data transfer causing the DTCCTj register value to change to 0 is performed while the
RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode, the interrupt request
corresponding to the activation source is generated for the CPU during DTC operation. However, no interrupt
request is generated for the CPU when the activation source is SSU/I2C bus transmit data empty or flash ready
status.
Interrupt requests for the CPU are affected by the I flag or interrupt control register. In chain transfers, whether
the interrupt request is generated or not is determined either by the number of transfer times specified for the
first type of the transfer or the RPTINT bit. When an interrupt request is generated for the CPU, the bit among
bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 3, 5, or 6) registers corresponding to the activation source
is set to 0 (activation disabled).
DTC activation source
generation
Read DTC vector
Read control data 1
Transfer data
Write back control data 1
Read control data 2
Data transfer
Write back control data 2
End of DTC transfers
Control data 1
CHNE = 1
Control data 2
CHNE = 0
DTC control data area
CHNE: Bit in DTCCRj register