R8C/36T-A Group
8. Watchdog Timer
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 81 of 728
Aug 05, 2011
8.3.3
When Count Source Protection Mode is Enabled
When count source protection mode is enabled, the count source for the watchdog timer is the low-speed on-
chip oscillator clock for the watchdog timer. If the CPU clock is stopped when a program runs out of control, a
clock will still be supplied to the watchdog timer.
Notes:
1. Only write to the WDTR register while the watchdog timer is counting.
2. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 at address 0FFFFh with a flash
programmer.
3. The CSPRO bit is set to 1 even if 0 is written to the CSPROINI bit in the OFS register. The CSPROINI bit cannot
be changed by a program. To set this bit, write 0 to bit 7 at address 0FFFFh with a flash programmer.
Table 8.4
Watchdog Timer Specifications when Count Source Protection Mode is Enabled
Item
Specification
Count source
Low-speed on-chip oscillator clock for the watchdog timer
Count operation
Decrement
Period
Count value of the watchdog timer (m)
Low-speed on-chip oscillator clock for the watchdog timer
m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register
Ex.: When the low-speed on-chip oscillator clock for the watchdog timer is 125 kHz and bits
WDTUFS1 and WDTUFS0 are 00b (03FFh), the period is approx. 8.2 ms.
Watchdog timer
initialization conditions
Reset
00h and then FFh are written to the WDTR register
(1) Underflow
Count start conditions
The operation of the watchdog timer after a reset is selected by the WDTON bit
(2) in the
OFS register (address 0FFFFh).
When the WDTON bit is 1 (watchdog timer is stopped after reset)
The watchdog timer and the prescaler are stopped after a reset, and only start counting
when the WDTS register is written.
When the WDTON bit is 0 (watchdog timer automatically starts after reset)
The watchdog timer and the prescaler automatically start counting after a reset.
Count stop condition
None (Once count has started, it will not stop even in wait mode or stop mode.)
Registers, bits
When the CSPRO bit in the CSPR register is set to 1 (count source protection mode
enabled)
(3), the following are automatically set:
The low-speed on-chip oscillator for the watchdog timer oscillates.
The RIS bit in the RISR register is set to 1 (watchdog timer reset).