R8C/36T-A Group
20. Serial Interface (UART2)
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 414 of 728
Aug 05, 2011
Figure 20.3
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
D0 D1 D2 D3 D4 D5 D6 D7
TC
TCLK
Stops because TE bit is set to 0
Data is set in U2TB register
Data transfer from U2TB register to UART2 transmit register
TC = TCLK = 2 (n + 1) / fj
fj: Frequency of U2BRG count source
(f1, f8, f32, or fC1)
n: Value set in U2BRG register
Transfer clock
TE bit in
U2C1 register
TI bit in
U2C1 register
CLK2
TXD2
TXEPT bit in
U2C0 register
CTS2
IR bit in
U2TIC register
Set to 0 by acknowledgment of an interrupt request or by a program
Stops because high level is applied to CTS2
1/fEXT
Dummy data is set in U2TB register
CLK2
RXD2
RTS2
RE bit in
U2C1 register
Data transfer from U2TB register to UART2 transmit register
Data read from U2RB register
fEXT: Frequency of external clock
Make sure the following conditions are met when the
CLK2 pin input is high before receiving data:
TE bit in U2C1 register = 1 (transmission enabled)
RE bit in U2C1 register = 1 (reception enabled)
Dummy data is written to U2TB register
Data transfer from UART2 receive
register to U2RB register
Set to 0 by acknowledgment of an interrupt request or by a program
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
D7
D6
TE bit in
U2C1 register
TI bit in
U2C1 register
OER bit in
U2RB register
IR bit in
U2RIC register
RI bit in
U2C1 register
The above diagram applies under the following conditions:
CKDIR bit in U2MR register = 0 (internal clock)
CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
CKPOL bit in U2C0 register = 0 (transmit data is output at the falling edge and
receive data is input at the rising edge of the transfer clock)
U2IRS bit in U2C1 register = 0 (interrupt request generation when the U2TB register is empty)
The above diagram applies under the following conditions:
CKDIR bit in U2MR register = 1 (external clock)
CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 1
(RTS function selected)
CKPOL bit in U2C0 register = 0 (transmit data is output at the falling edge and
receive data is input at the rising edge of the transfer clock)
Received data is acquired
Low level is applied when U2RB register is read
(1) Transmit timing example (internal clock selected)
(2) Receive timing example (external clock selected)