12
Datasheet
Introduction
SIMD integer, and memory management operations. In addition, SSE3 instructions have been
added to further extend the capabilities of Intel processor technology. Other processor
enhancements include core frequency improvements and microarchitectural improvements.
64-bit Intel Xeon processors with 2 MB L2 cache supports Intel Extended Memory 64 Technology
(Intel EM64T) as an enhancement to Intel's IA-32 architecture. This enhancement allows the
processor to execute operating systems and applications written to take advantage of the 64-bit
extension technology. Further details on Intel Extended Memory 64 Technology and its
programming model can be found in the 64-bit Intel Extended Memory 64 Technology Software
Developer's Guide at http://developer.intel.com/technology/64bitextensions/.
64-bit Intel Xeon processors with 2 MB L2 cache are intended for high performance workstation
and server systems with up to two processors on one system bus. The 64-bit Intel Xeon MV 3.20
GHz processor is a mid-voltage processor intended for volumetrically constrained platforms. The
64-bit Intel Xeon LV 3 GHz processor is a low-voltage, low-power processor intended for
embedded and volumetrically constrained platforms. These processors are packaged in a 604-pin
Flip Chip Micro Pin Grid Array (FC-mPGA4) package and use a surface mount Zero Insertion
Force (ZIF) socket (mPGA604).
64-bit Intel Xeon processor with 2 MB L2 cache-based platforms implement independent power
planes for each system bus agent. As a result, the processor core voltage (VCC) and system bus
termination voltage (VTT) must connect to separate supplies. The processor core voltage utilizes
power delivery guidelines denoted by VRM 10.1 and the associated load line (see Voltage
Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.1 Design
Guidelines for further details). Implementation details can be obtained by referring to the
applicable platform design guidelines. Cost-reduced power delivery systems may be possible for
mid-voltage (MV) and low-voltage (LV) processors.
The 64-bit Intel Xeon processor with 2 MB L2 cache uses a scalable system bus protocol referred
to as the “system bus” in this document. The system bus utilizes a split-transaction, deferred reply
protocol. The system bus uses Source-Synchronous Transfer (SST) of address and data to improve
performance. The processor transfers data four times per bus clock (4X data transfer rate, as in
AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus
clock and is referred to as a ‘double-clocked’ or the 2X address bus. In addition, the Request Phase
completes in one clock cycle. Working together, the 4X data bus and 2X address bus provide a data
bus bandwidth of up to 6.4 GBytes/second (6400 MBytes/second). Finally, the system bus is also
used to deliver interrupts.
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the asserted
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
Table 1-1. Features of the 64-bit Intel Xeon Processor with 2 MB L2 Cache
# of Supported
Symmetric
Agents
L2 Advanced
Transfer
Cache
Front Side
Bus
Frequency
Package
64-bit Intel Xeon processor
with 2 MB L2 cache
64-bit Intel Xeon MV 3.20
GHz processor
64-bit Intel Xeon LV 3 GHz
processor
1 - 2
2 MB
800 MHz
604-pin FC-
mPGA4