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参数资料
| 型号： | RK80546KG0802MM |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 3000 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO PGA-604 |
| 文件页数： | 49/106页 |
| 文件大小： | 4724K |
| 代理商： | RK80546KG0802MM |
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Datasheet
47
Signal Definitions
BPRI#
I
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
processor front side bus. It must connect the appropriate pins of all
processor front side bus agents. Observing BPRI# active (as asserted by
the priority agent) causes all other agents to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The priority
agent keeps BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
4
BR0#
BR[1:3]#1
I/O
I
BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The
BREQ[3:0]# signals are interconnected in a rotating manner to individual
processor pins. The tables below provide the rotating interconnect
between the processor and bus signals for 2-way systems.
During power-on configuration, the central agent must assert the BR0# bus
signal. All symmetric agents sample their BR[3:0]# pins on the active-to-
inactive transition of RESET#. The pin which the agent samples asserted
determines it’s agent ID.
These signals do not have on-die termination and must be terminated
at the end agent.
1,4
BSEL[1:0]
O
The BCLK[1:0] frequency select signals BSEL[1:0] are used to select the
processor input clock frequency. Table defines the possible combinations
of the signals and the frequency associated with each combination. The
required frequency is determined by the processors, chipset, and clock
synthesizer. All front side bus agents must operate at the same frequency.
The 64-bit Intel Xeon processor with 2 MB L2 cache currently operates at a
800 MHz front side bus frequency (200 MHz BCLK[1:0] frequency). For
more information about these pins, including termination
recommendations, refer to the appropriate platform design guideline.
COMP[1:0]
I
COMP[1:0] must be terminated to VSS on the baseboard using precision
resistors. These inputs configure the GTL+ drivers of the processor. Refer
to the appropriate platform design guidelines for implementation details.
Table 4-1. Signal Definitions (Sheet 3 of 10)
Name
Type
Description
Notes
BR[1:0]# Signals Rotating Interconnect, 2-way system
BR2# and BR3# must not be utilized in 2-way platform designs. However,
they must still be terminated.
Bus Signal
Agent 0 Pins
Agent 1 Pins
BREQ0#
BR0#
BR1#
BREQ1#
BR1#
BR0#
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RK80546KG0802MMS L7ZF | 制造商:Intel 功能描述:MPU Xeon NetBurst 64-Bit 90nm 3GHz 604-Pin FCmPGA4 制造商:Intel 功能描述:XEON 3E GHZ,2M,800MHZ,FC MPGA4 - Trays |
| RK80546KG0881M S L7PF | 制造商:Intel 功能描述:INTEL XEON, 3.2DGHZ,1M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG0882MMS L7ZE | 制造商:Intel 功能描述:XEON 3.2,2M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG1041M | 制造商:Rochester Electronics LLC 功能描述:XEON 3.6GHZ,1M,800MHZ,FC MPGA4 - Bulk |
| RK80546KG1041M S L7PH | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU XEON 90NM 3.6GHZ 604PIN PGA - Trays |
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