28
Datasheet
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processors. These specifications are based
on silicon characterization, however they may be updated as further data becomes available.
2. Each processor is programmed with a maximum valid voltage identification (VID) values, which is set at
manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Please
note this differs from the VID employed by the processor during a power management event (Thermal
Monitor 2, Enhanced Intel SpeedStep
Technology, or Enhanced HALT Power Down State).
3. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See
Section 2.4 for more information.
4. The voltage specification requirements are measured across vias on the platform for the VCCSENSE and
VSSSENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 M
minimum impedance. The maximum length of ground wire on the probe should be
less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.
5. Refer to Table 2-9 and corresponding Figure 2-4. The processor should not be subjected to any static VCC level that exceeds the VCC_MAX associated with any particular current. Failure to adhere to this specification
can shorten processor lifetime.
6. Minimum VCC and maximum ICC are specified at the maximum processor case temperature (TCASE) shown
in Table 6-1. ICC_MAX is specified at the relative VCC_MAX point on the VCC load line. The processor is capable of drawing ICC_MAX for up to 10 ms. Refer to Figure 2-2 for further details on the average processor current draw over various time durations.
7. FMB is the flexible motherboard guideline. These guidelines are for estimation purposes only. See
8. This specification represents the VCC reduction due to each VID transition. See Section 2.4. 9. This specification refers to the potential total reduction of the load line due to VID transitions below the
specified VID.
10.VTT must be provided via a separate voltage source and must not be connected to VCC. This specification is
measured at the pin.
11.Baseboard bandwidth is limited to 20 MHz.
12.This specification refers to a single processor with RTT enabled. Please note the end agent and middle agent
may not require ITT(max) simultaneously. This parameter is based on design characterization and not tested.
13.This specification refers to a single processor with RTT disabled. Please note the end agent and middle agent
may not require ITT(max) simultaneously.
14.These specifications apply to the PLL power pins VCCA, VCCIOPLL, and VSSA. See
Section 2.3.2 for
details. These parameters are based on design characterization and are not tested.
15.This specification represents a total current for all GTLREF pins.
16.The current specified is also for HALT State.
17.The maximum instantaneous current the processor will draw while the thermal control circuit is active as
indicated by the assertion of the PROCHOT# signal is the maximum ICC for the processor.
18.ICC_TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of
drawing indefinitely and should be used for the voltage regulator temperature assessment. The voltage
regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the
processor of a thermal excursion. Please see the applicable design guidelines for further details. The
processor is capable of drawing ICC_TDC indefinitely. Refer to
Figure 2-2 for further details on the average
processor craw over various time durations. This parameter is based on design characterization and is not
tested.