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参数资料
| 型号： | RK80546KG0802MM |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 3000 MHz, MICROPROCESSOR, CPGA604 |
| 封装： | FLIP CHIP, MICRO PGA-604 |
| 文件页数： | 8/106页 |
| 文件大小： | 4724K |
| 代理商： | RK80546KG0802MM |
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Datasheet
105
9
Debug Tools Specifications
Please refer to the ITP700 Debug Port Design Guide for information regarding debug tool
specifications. Section 1.2 provides collateral details.
9.1
Debug Port System Requirements
The 64-bit Intel Xeon processor with 2 MB L2 cache debug port is the command and control
interface for the In-Target Probe (ITP) debugger. The ITP enables run-time control of the
processors for system debug. The debug port, which is connected to the front side bus, is a
combination of the system, JTAG and execution signals. There are several mechanical, electrical
and functional constraints on the debug port that must be followed. The mechanical constraint
requires the debug port connector to be installed in the system with adequate physical clearance.
Electrical constraints exist due to the mixed high and low speed signals of the debug port for the
processor. While the JTAG signals operate at a maximum of 75 MHz, the execution signals operate
at the common clock front side bus frequency (200 MHz). The functional constraint requires the
debug port to use the JTAG system via a handshake and multiplexing scheme.
In general, the information in this chapter may be used as a basis for including all run-control tools
in 64-bit Intel Xeon processor with 2 MB L2 cache-based system designs, including tools from
vendors other than Intel.
Note:
The debug port and JTAG signal chain must be designed into the processor board to utilize the ITP
for debug purposes.
9.2
Target System Implementation
9.2.1
System Implementation
Specific connectivity and layout guidelines for the Debug Port are provided in the ITP700 Debug
Port Design Guide.
9.3
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use
in debugging 64-bit Intel Xeon processor with 2 MB L2 cache-based systems. Tektronix* and
Agilent* should be contacted to obtain specific information about their logic analyzer interfaces.
The following information is general in nature. Specific information must be obtained from the
logic analyzer vendor.
Due to the complexity of 64-bit Intel Xeon processor with 2 MB L2 cache-based multiprocessor
systems, the LAI is critical in providing the ability to probe and capture front side bus signals.
There are two sets of considerations to keep in mind when designing a 64-bit Intel Xeon processor
with 2 MB L2 cache-based system that can make use of an LAI: mechanical and electrical.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RK80546KG0802MMS L7ZF | 制造商:Intel 功能描述:MPU Xeon NetBurst 64-Bit 90nm 3GHz 604-Pin FCmPGA4 制造商:Intel 功能描述:XEON 3E GHZ,2M,800MHZ,FC MPGA4 - Trays |
| RK80546KG0881M S L7PF | 制造商:Intel 功能描述:INTEL XEON, 3.2DGHZ,1M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG0882MMS L7ZE | 制造商:Intel 功能描述:XEON 3.2,2M,800MHZ,FC-MPGA4 - Trays |
| RK80546KG1041M | 制造商:Rochester Electronics LLC 功能描述:XEON 3.6GHZ,1M,800MHZ,FC MPGA4 - Bulk |
| RK80546KG1041M S L7PH | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU XEON 90NM 3.6GHZ 604PIN PGA - Trays |
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